对称型fir滤波器vhdl源代码.txt

对称型线性相位FIR滤波器的VHDL源程序

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----------       对称型FIR滤波器       ----------
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
PACKAGE coeffs IS
  TYPE coef_arr IS ARRAY(0 TO 2) OF SIGNED (8 DOWNTO 0);
  CONSTANT coefs: coef_arr:=("111111001","111111011","000001101");
END coeffs;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
USE work.coeffs.all;

ENTITY fir IS
  PORT(clk,reset : IN STD_LOGIC;
          sample : IN SIGNED (7 DOWNTO 0);
          result : OUT SIGNED (16 DOWNTO 0));
END fir;

ARCHITECTURE beh OF fir IS
BEGIN
  main : PROCESS(clk,reset)
    TYPE shift_arr IS ARRAY (4 DOWNTO 0) OF SIGNED (7 DOWNTO 0);
    VARIABLE tmp,old : SIGNED(7 DOWNTO 0);  --tmp用于保存本次采样值，old用于保存在shift中的第i个采样
    VARIABLE pro : SIGNED(16 DOWNTO 0);  --pro用于记录U(k-i)和h(i)的乘积
    VARIABLE acc : SIGNED(16 DOWNTO 0);  --acc用于记录累加值
    VARIABLE shift : shift_arr;

BEGIN
  IF reset = '1' THEN
    result<=(others=>'0');  --将结果清零
    FOR i IN 0 TO 3 LOOP  --将寄存器shift清零
    shift(i):=(others=>'0');  --由于shift(4)只用于存放需要丢弃的采样值，所以无需清零
    END LOOP;
  ELSIF clk'EVENT AND clk='1' THEN
    tmp:=sample;  --取当前采样值
    pro:=(tmp+shift(3))*coefs(0);
    acc:=pro;
    
    FOR i IN 0 TO 0 LOOP
      old:=shift(i)+shift(2-i);
      pro:=old*coefs(i+1);
      acc:=acc+pro;  --累计最近L次采样值
    END LOOP;
    acc:=acc+shift(1)*coefs(2);
    FOR i IN 3 DOWNTO 0 LOOP  --shift寄存器移位
      shift(i+1):=shift(i);
    END LOOP;
    shift(0):=tmp;  --将当前采样值保存在shift(0)中，
                    --以便下次采样时，shift中保存的是最近的L次采样值，将结果送给result
    result<=acc;
  END IF;
END PROCESS main;
END beh;