📄 serial_implementation.vhdl
字号:
LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;ENTITY serial_implementation IS GENERIC (WIDTH:INTEGER:=8; N:INTEGER:=4); PORT (reset,start,clk:STD_LOGIC; x:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0); finished:OUT STD_LOGIC);END serial_implementation;ARCHITECTURE arch_serial_implementation OF serial_implementation ISTYPE array_type IS ARRAY(0 TO N-1) OF STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--CONSTANT const_array:array_type:=("11011000",-- "00011101",-- "00011101",-- "11011000");CONSTANT const_array:array_type:=("00000001", "00000001", "00000001", "00000001");SIGNAL sample_array:array_type;SIGNAL y_signal:SIGNED(2*WIDTH-1 DOWNTO 0);SIGNAL count:INTEGER RANGE 0 TO N;BEGIN FIR_process: PROCESS(reset,clk,start) BEGIN IF (reset='1') THEN y_signal<=(OTHERS=>'0'); sample_array(1)<="00001111"; sample_array(2)<="00111100"; sample_array(3)<="00011100";-- sample_array(1)<="00000001";-- sample_array(2)<="00000001";-- sample_array(3)<="00000001"; ELSIF (clk'EVENT AND clk='1') THEN IF (start='1') THEN count<=0; finished<='0'; sample_array(0)<=x; y_signal<=(OTHERS=>'0'); ELSIF (count<N) THEN y_signal<=y_signal+SIGNED(sample_array(count))* SIGNED(const_array(count)); IF (count=N-1)THEN FOR i IN sample_array'HIGH DOWNTO 2 LOOP sample_array(i)<=sample_array(i-1); END LOOP; sample_array(1)<=x; finished<='1'; END IF; count<=count+1; END IF; END IF; END PROCESS FIR_process; y<=STD_LOGIC_VECTOR(y_signal);END arch_serial_implementation;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -