distributed_implementation.vhdl

VHDL 实现 有限冲击响应滤波器的设计（分布式）

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.math_real.ALL;

ENTITY distributed_implementation IS
   GENERIC (WIDTH:INTEGER:=8;
            N:INTEGER:=4);
   PORT (reset,start,clk:STD_LOGIC;
         x:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
         y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0);
         finished:OUT STD_LOGIC);
END distributed_implementation;

ARCHITECTURE arch_distributed_implementation OF distributed_implementation IS
TYPE array_type IS ARRAY(0 TO N-1) OF
              STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);

COMPONENT FIR_ROM IS
   GENERIC (ADDRESSES:INTEGER;
            WIDTH:INTEGER);
   PORT (ADDR:IN INTEGER RANGE 0 to ADDRESSES-1;
         DATA:OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0));
END COMPONENT;
CONSTANT zeros:SIGNED(WIDTH-1 DOWNTO 0):=(OTHERS=>'0');
SIGNAL sample_array:array_type;
SIGNAL y_signal:SIGNED(2*WIDTH-1 DOWNTO 0);
SIGNAL count:INTEGER RANGE 1 TO WIDTH+1;
SIGNAL ROM_ADDR:INTEGER RANGE 0 TO 15;--INTEGER(2**N)-1;
SIGNAL DATA:STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
SIGNAL started:STD_LOGIC;

BEGIN
   FIR_constants:
   FIR_ROM
      GENERIC MAP(ADDRESSES=>INTEGER(2**N),WIDTH=>WIDTH)
      PORT MAP(ADDR=>ROM_ADDR,DATA=>DATA);
   FIR_process:
   PROCESS(reset,clk,start)
   VARIABLE addr_vector:UNSIGNED(N-1 DOWNTO 0);
   
   BEGIN
      IF (reset='1') THEN
         y_signal<=(OTHERS=>'0');
         sample_array(1)<="00001111";
         sample_array(2)<="00111100";
         sample_array(3)<="00011100";
--         sample_array(1)<="00000001";
--         sample_array(2)<="00000001";
--         sample_array(3)<="00000001";
         finished<='0';
         started<='0';
      ELSIF (clk'EVENT AND clk='1') THEN
         IF (start='1') THEN
            count<=1;
            finished<='0';
            sample_array(0)<=x;
            y_signal<=(OTHERS=>'0');
            FOR i IN N-1 DOWNTO 1 LOOP
	             addr_vector(i):=sample_array(i)(0);
	          END LOOP;
	          addr_vector(0):=x(0);
            ROM_ADDR<=TO_INTEGER(addr_vector);
            started<='1';
         ELSIF ((count<WIDTH+1) AND (started='1')) THEN
            IF (count<WIDTH) THEN
               FOR i IN N-1 DOWNTO 0 LOOP
                  addr_vector(i):=sample_array(i)(count);
               END LOOP;
               ROM_ADDR<=TO_INTEGER(addr_vector);
               y_signal<=y_signal(2*WIDTH-1)&y_signal(2*WIDTH-1 DOWNTO 1)+(SIGNED(DATA)&zeros);
             ELSE
               FOR i IN sample_array'HIGH DOWNTO 2 LOOP
                  sample_array(i)<=sample_array(i-1);
               END LOOP;
               sample_array(1)<=x;
               finished<='1';
               started<='0';
            END IF;
            count<=count+1;
         END IF;
      END IF;
   END PROCESS FIR_process;
   y<=STD_LOGIC_VECTOR(y_signal(2*WIDTH-1)&y_signal(2*WIDTH-1 DOWNTO 1));
END arch_distributed_implementation;