📄 direct_implementation.vhdl
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LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;ENTITY direct_implementation IS GENERIC (WIDTH:INTEGER:=8; N:INTEGER:=4); PORT (reset,start:STD_LOGIC; x:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0));END direct_implementation;ARCHITECTURE arch_direct_implementation OF direct_implementation ISTYPE const_array_type IS ARRAY(0 TO N-1) OF STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);TYPE sample_array_type IS ARRAY(1 TO N-1) OF STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--CONSTANT const_array:mem_array:=("11011000",-- "00011101",-- "00011101",-- "11011000");CONSTANT const_array:const_array_type:=("00000001", "00000001", "00000001", "00000001");SIGNAL sample_array:sample_array_type;BEGIN FIR_process: PROCESS(reset,start) VARIABLE y_var:SIGNED(2*WIDTH-1 DOWNTO 0); BEGIN IF (reset='1') THEN y_var:=(OTHERS=>'0'); sample_array(1)<="00001111"; sample_array(2)<="00111100"; sample_array(3)<="00011100";-- sample_array(1)<="00000001";-- sample_array(2)<="00000001";-- sample_array(3)<="00000001"; ELSIF (start='1') THEN y_var:=(OTHERS=>'0'); y_var:=SIGNED(x)*SIGNED(const_array(0)); FOR i IN 1 TO sample_array'HIGH LOOP y_var:=y_var+SIGNED(sample_array(i))* SIGNED(const_array(i)); END LOOP; FOR i IN sample_array'HIGH DOWNTO 2 LOOP sample_array(i)<=sample_array(i-1); END LOOP; sample_array(1)<=x; END IF; y<=STD_LOGIC_VECTOR(y_var); END PROCESS FIR_process;END arch_direct_implementation;
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