de2_board.ptf.5.00

Altera FPGA 上利用nios嵌入式处理器实现USB的通信控制

         class_version = "2.0";
         WIZARD_SCRIPT_ARGUMENTS 
         {
            CONSTANTS 
            {
               CONSTANT debug_on
               {
                  value = "0";
                  comment = "Enable debug features";
               }
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Is_Enabled = "0";
         }
      }
      SOFTWARE_COMPONENT altera_plugs_library
      {
         class = "altera_plugs_library";
         class_version = "2.1";
         WIZARD_SCRIPT_ARGUMENTS 
         {
            CONSTANTS 
            {
               CONSTANT PLUGS_PLUG_COUNT
               {
                  value = "5";
                  comment = "Maximum number of plugs";
               }
               CONSTANT PLUGS_ADAPTER_COUNT
               {
                  value = "2";
                  comment = "Maximum number of adapters";
               }
               CONSTANT PLUGS_DNS
               {
                  value = "1";
                  comment = "Have routines for DNS lookups";
               }
               CONSTANT PLUGS_PING
               {
                  value = "1";
                  comment = "Respond to icmp echo (ping) messages";
               }
               CONSTANT PLUGS_TCP
               {
                  value = "1";
                  comment = "Support tcp in/out connections";
               }
               CONSTANT PLUGS_IRQ
               {
                  value = "1";
                  comment = "Run at interrupte level";
               }
               CONSTANT PLUGS_DEBUG
               {
                  value = "1";
                  comment = "Support debug routines";
               }
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Is_Enabled = "1";
         }
      }
      MASTER custom_instruction_master
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "8";
            Max_Address_Width = "8";
            Base_Address = "N/A";
            Is_Visible = "0";
            Is_Custom_Instruction = "0";
            Is_Enabled = "0";
         }
      }
      PORT_WIRING 
      {
         PORT jtag_debug_trigout
         {
            width = "1";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_clk
         {
            width = "1";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_data
         {
            width = "18";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT clkx2
         {
            width = "1";
            direction = "input";
            Is_Enabled = "0";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL aaa
            {
               format = "Logic";
               name = "d_irq";
               radix = "hexadecimal";
            }
            SIGNAL aab
            {
               format = "Logic";
               name = "d_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aac
            {
               format = "Logic";
               name = "d_address";
               radix = "hexadecimal";
            }
            SIGNAL aad
            {
               format = "Logic";
               name = "d_byteenable";
               radix = "hexadecimal";
            }
            SIGNAL aae
            {
               format = "Logic";
               name = "d_read";
               radix = "hexadecimal";
            }
            SIGNAL aaf
            {
               format = "Logic";
               name = "d_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aag
            {
               format = "Logic";
               name = "d_write";
               radix = "hexadecimal";
            }
            SIGNAL aah
            {
               format = "Logic";
               name = "d_writedata";
               radix = "hexadecimal";
            }
            SIGNAL aai
            {
               format = "Logic";
               name = "i_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aaj
            {
               format = "Logic";
               name = "i_address";
               radix = "hexadecimal";
            }
            SIGNAL aak
            {
               format = "Logic";
               name = "i_read";
               radix = "hexadecimal";
            }
            SIGNAL aal
            {
               format = "Logic";
               name = "i_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aam
            {
               format = "Divider";
               name = "common";
               radix = "";
            }
            SIGNAL aan
            {
               format = "Logic";
               name = "clk";
               radix = "hexadecimal";
            }
            SIGNAL aao
            {
               format = "Logic";
               name = "reset_n";
               radix = "hexadecimal";
            }
            SIGNAL aap
            {
               format = "Logic";
               name = "F_pcb_nxt";
               radix = "hexadecimal";
            }
            SIGNAL aaq
            {
               format = "Logic";
               name = "F_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aar
            {
               format = "Logic";
               name = "F_vinst";
               radix = "ascii";
            }
            SIGNAL aas
            {
               format = "Logic";
               name = "D_vinst";
               radix = "ascii";
            }
            SIGNAL aat
            {
               format = "Logic";
               name = "R_vinst";
               radix = "ascii";
            }
            SIGNAL aau
            {
               format = "Logic";
               name = "E_vinst";
               radix = "ascii";
            }
            SIGNAL aav
            {
               format = "Logic";
               name = "W_vinst";
               radix = "ascii";
            }
            SIGNAL aaw
            {
               format = "Logic";
               name = "F_valid";
               radix = "hexadecimal";
            }
            SIGNAL aax
            {
               format = "Logic";
               name = "D_valid";
               radix = "hexadecimal";
            }
            SIGNAL aay
            {
               format = "Logic";
               name = "R_valid";
               radix = "hexadecimal";
            }
            SIGNAL aaz
            {
               format = "Logic";
               name = "E_valid";
               radix = "hexadecimal";
            }
            SIGNAL aba
            {
               format = "Logic";
               name = "W_valid";
               radix = "hexadecimal";
            }
            SIGNAL abb
            {
               format = "Logic";
               name = "D_wr_dst_reg";
               radix = "hexadecimal";
            }
            SIGNAL abc
            {
               format = "Logic";
               name = "D_dst_regnum";
               radix = "hexadecimal";
            }
            SIGNAL abd
            {
               format = "Logic";
               name = "W_wr_data";
               radix = "hexadecimal";
            }
            SIGNAL abe
            {
               format = "Logic";
               name = "F_iw";
               radix = "hexadecimal";
            }
            SIGNAL abf
            {
               format = "Logic";
               name = "D_iw";
               radix = "hexadecimal";
            }
         }
      }
      MASTER tightly_coupled_instruction_master_0
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER data_master2
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writeable = "1";
         }
      }
      MASTER tightly_coupled_data_master_0
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writeable = "1";
         }
      }
      MASTER tightly_coupled_data_master_1
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writeable = "1";
         }
      }
      MASTER tightly_coupled_data_master_2
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writeable = "1";
         }
      }
      MASTER tightly_coupled_data_master_3
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writeable = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_1
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }