de2_board.fit.rpt

Altera FPGA 上利用nios嵌入式处理器实现USB的通信控制

+------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                        ;
+------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                               ; Setting                        ; Default Value                  ;
+------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                               ; EP2C35F672C6                   ;                                ;
; SignalProbe signals routed during normal compilation ; Off                            ; Off                            ;
; Use smart compilation                                ; Off                            ; Off                            ;
; Router Timing Optimization Level                     ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                          ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                             ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                 ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                          ; Off                            ; Off                            ;
; PowerPlay Power Optimization                         ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                      ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing           ; On                             ; On                             ;
; Limit to One Fitting Attempt                         ; Off                            ; Off                            ;
; Final Placement Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations          ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                        ; 1                              ; 1                              ;
; PCI I/O                                              ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                            ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                   ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/Cyclone II       ; Auto                           ; Auto                           ;
; Auto Delay Chains                                    ; On                             ; On                             ;
; Auto Merge PLLs                                      ; On                             ; On                             ;
; Fitter Effort                                        ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                      ; Normal                         ; Normal                         ;
; Auto Global Clock                                    ; On                             ; On                             ;
; Auto Global Register Control Signals                 ; On                             ; On                             ;
+------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve nCEO pin after configuration         ; As output driving ground ;
; Reserve ASDO pin after configuration.        ; As input tri-stated      ;
; Reserve all unused pins                      ; As input tri-stated      ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                                                                                                                                       ;
+--------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+--------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node                                                                                                                                 ; Action          ; Operation        ; Reason                                 ; Node Port ; Destination Node                                                                                                               ; Destination Port ;
+--------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+--------------------------------------------------------------------------------------------------------------------------------+------------------+
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle                    ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; FL_DQ[7]                                                                                                                       ; OE               ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle                    ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_1 ; REGOUT           ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle                    ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_2 ; REGOUT           ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle                    ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_3 ; REGOUT           ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle                    ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_4 ; REGOUT           ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle                    ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_5 ; REGOUT           ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle                    ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_6 ; REGOUT           ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle                    ; Duplicated      ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_7 ; REGOUT           ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_1       ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; FL_DQ[6]                                                                                                                       ; OE               ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_2       ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; FL_DQ[5]                                                                                                                       ; OE               ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_3       ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; FL_DQ[4]                                                                                                                       ; OE               ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_4       ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; FL_DQ[3]                                                                                                                       ; OE               ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_5       ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; FL_DQ[2]                                                                                                                       ; OE               ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_6       ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; FL_DQ[1]                                                                                                                       ; OE               ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_7       ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT    ; FL_DQ[0]                                                                                                                       ; OE               ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[0] ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ; FL_DQ[0]                                                                                                                       ; DATAIN           ;
; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[1] ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ; FL_DQ[1]                                                                                                                       ; DATAIN           ;