de2_board.fit.summary

Altera FPGA 上利用nios嵌入式处理器实现USB的通信控制

Fitter Status : Successful - Thu Nov 17 16:24:33 2005
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : DE2_Board
Top-level Entity Name : DE2_Board_top
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Preliminary
Total logic elements : 1,493 / 33,216 ( 4 % )
Total registers : 770
Total pins : 36 / 475 ( 8 % )
Total virtual pins : 0
Total memory bits : 177,152 / 483,840 ( 37 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )