de2_board.fit.eqn

Altera FPGA 上利用nios嵌入式处理器实现USB的通信控制

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--YB1_safe_q[9] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[9] at LCFF_X53_Y16_N19
YB1_safe_q[9] = DFFEAS(YB1_counter_comb_bita9, GLOBAL(A1L16), KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[8] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[8] at LCFF_X53_Y16_N17
YB1_safe_q[8] = DFFEAS(YB1_counter_comb_bita8, GLOBAL(A1L16), KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[7] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[7] at LCFF_X53_Y16_N15
YB1_safe_q[7] = DFFEAS(YB1_counter_comb_bita7, GLOBAL(A1L16), KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[6] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[6] at LCFF_X53_Y16_N13
YB1_safe_q[6] = DFFEAS(YB1_counter_comb_bita6, GLOBAL(A1L16), KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[5] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[5] at LCFF_X53_Y16_N11
YB1_safe_q[5] = DFFEAS(YB1_counter_comb_bita5, GLOBAL(A1L16), KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[4] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[4] at LCFF_X53_Y16_N9
YB1_safe_q[4] = DFFEAS(YB1_counter_comb_bita4, GLOBAL(A1L16), KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[3] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[3] at LCFF_X53_Y16_N7
YB1_safe_q[3] = DFFEAS(YB1_counter_comb_bita3, GLOBAL(A1L16), KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[2] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[2] at LCFF_X53_Y16_N5
YB1_safe_q[2] = DFFEAS(YB1_counter_comb_bita2, GLOBAL(A1L16), KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[1] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[1] at LCFF_X53_Y16_N3
YB1_safe_q[1] = DFFEAS(YB1_counter_comb_bita1, GLOBAL(A1L16), KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[0] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[0] at LCFF_X53_Y16_N1
YB1_safe_q[0] = DFFEAS(YB1_counter_comb_bita0, GLOBAL(A1L16), KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_counter_comb_bita0 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita0 at LCCOMB_X53_Y16_N0
YB1_counter_comb_bita0 = YB1_safe_q[0] $ VCC;

--YB1L2 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita0~COUT at LCCOMB_X53_Y16_N0
YB1L2 = CARRY(YB1_safe_q[0]);


--YB1_counter_comb_bita1 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita1 at LCCOMB_X53_Y16_N2
YB1_counter_comb_bita1 = YB1_safe_q[1] & !YB1L2 # !YB1_safe_q[1] & (YB1L2 # GND);

--YB1L4 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita1~COUT at LCCOMB_X53_Y16_N2
YB1L4 = CARRY(!YB1L2 # !YB1_safe_q[1]);


--YB1_counter_comb_bita2 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita2 at LCCOMB_X53_Y16_N4
YB1_counter_comb_bita2 = YB1_safe_q[2] & (YB1L4 $ GND) # !YB1_safe_q[2] & !YB1L4 & VCC;

--YB1L6 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita2~COUT at LCCOMB_X53_Y16_N4
YB1L6 = CARRY(YB1_safe_q[2] & !YB1L4);


--YB1_counter_comb_bita3 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita3 at LCCOMB_X53_Y16_N6
YB1_counter_comb_bita3 = YB1_safe_q[3] & !YB1L6 # !YB1_safe_q[3] & (YB1L6 # GND);

--YB1L8 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita3~COUT at LCCOMB_X53_Y16_N6
YB1L8 = CARRY(!YB1L6 # !YB1_safe_q[3]);


--YB1_counter_comb_bita4 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita4 at LCCOMB_X53_Y16_N8
YB1_counter_comb_bita4 = YB1_safe_q[4] & (YB1L8 $ GND) # !YB1_safe_q[4] & !YB1L8 & VCC;

--YB1L10 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita4~COUT at LCCOMB_X53_Y16_N8
YB1L10 = CARRY(YB1_safe_q[4] & !YB1L8);


--YB1_counter_comb_bita5 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita5 at LCCOMB_X53_Y16_N10
YB1_counter_comb_bita5 = YB1_safe_q[5] & !YB1L10 # !YB1_safe_q[5] & (YB1L10 # GND);

--YB1L12 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita5~COUT at LCCOMB_X53_Y16_N10
YB1L12 = CARRY(!YB1L10 # !YB1_safe_q[5]);


--YB1_counter_comb_bita6 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita6 at LCCOMB_X53_Y16_N12
YB1_counter_comb_bita6 = YB1_safe_q[6] & (YB1L12 $ GND) # !YB1_safe_q[6] & !YB1L12 & VCC;

--YB1L14 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita6~COUT at LCCOMB_X53_Y16_N12
YB1L14 = CARRY(YB1_safe_q[6] & !YB1L12);


--YB1_counter_comb_bita7 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita7 at LCCOMB_X53_Y16_N14
YB1_counter_comb_bita7 = YB1_safe_q[7] & !YB1L14 # !YB1_safe_q[7] & (YB1L14 # GND);

--YB1L16 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita7~COUT at LCCOMB_X53_Y16_N14
YB1L16 = CARRY(!YB1L14 # !YB1_safe_q[7]);


--YB1_counter_comb_bita8 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita8 at LCCOMB_X53_Y16_N16
YB1_counter_comb_bita8 = YB1_safe_q[8] & (YB1L16 $ GND) # !YB1_safe_q[8] & !YB1L16 & VCC;

--YB1L18 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita8~COUT at LCCOMB_X53_Y16_N16
YB1L18 = CARRY(YB1_safe_q[8] & !YB1L16);


--YB1_counter_comb_bita9 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita9 at LCCOMB_X53_Y16_N18
YB1_counter_comb_bita9 = YB1_safe_q[9] & !YB1L18 # !YB1_safe_q[9] & (YB1L18 # GND);

--YB1L22 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita9~COUT at LCCOMB_X53_Y16_N18
YB1L22 = CARRY(!YB1L18 # !YB1_safe_q[9]);


--YB1L20 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita9~9 at LCCOMB_X53_Y16_N20
YB1L20 = !YB1L22;


--C1_inst4 is delay_reset_block:inst3|inst4 at LCCOMB_X53_Y16_N30
C1_inst4 = !YB1L20 # !KEY[0];


--A1L7 is altera_internal_jtag~TDO at JTAG_X1_Y19_N0
A1L7 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L15);

--A1L8 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y19_N0
A1L8 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L15);

--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y19_N0
A1L5 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L15);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y19_N0
altera_internal_jtag = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L15);


--W1_tri_state_bridge_0_avalon_slave_arb_addend[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[1] at LCFF_X40_Y16_N25
W1_tri_state_bridge_0_avalon_slave_arb_addend[1] = DFFEAS(W1L125, GLOBAL(A1L16), GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--H1_F_pc[20] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[20] at LCFF_X41_Y22_N17
H1_F_pc[20] = AMPP_FUNCTION(A1L16, H1L593, E1L4, H1_W_valid);


--H1_i_read is DE2_Board:inst|cpu_0:the_cpu_0|i_read at LCFF_X40_Y17_N15
H1_i_read = AMPP_FUNCTION(A1L16, H1_i_read_nxt, E1L4);


--W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] at LCFF_X40_Y17_N25
W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L16), GLOBAL(E1L4),  ,  , W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0],  ,  , VCC);


--W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] at LCFF_X40_Y17_N5
W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEAS(W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in, GLOBAL(A1L16), GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1L28 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~57 at LCCOMB_X40_Y17_N24
W1L28 = !W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] & !H1_i_read & !W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & H1_F_pc[20];


--W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_slavearbiterlockenable at LCFF_X40_Y17_N7
W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable = DFFEAS(W1L150, GLOBAL(A1L16), GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 at LCFF_X41_Y18_N27
W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 = DFFEAS(W1L66, GLOBAL(A1L16), GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--H1_W_alu_result[22] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[22] at LCFF_X41_Y22_N25
H1_W_alu_result[22] = AMPP_FUNCTION(A1L16, H1L735, H1_E_shift_rot_result[22], E1L4, H1L127, H1_R_ctrl_shift_rot);


--H1_d_read is DE2_Board:inst|cpu_0:the_cpu_0|d_read at LCFF_X41_Y20_N21
H1_d_read = AMPP_FUNCTION(A1L16, H1_d_read_nxt, E1L4);


--AB1_d_write is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|d_write at LCFF_X41_Y20_N1
AB1_d_write = AMPP_FUNCTION(A1L16, H1_d_write_nxt, E1L4);


--W1_cpu_0_data_master_requests_cfi_flash_0_s1 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_0_s1 at LCCOMB_X37_Y18_N16
W1_cpu_0_data_master_requests_cfi_flash_0_s1 = H1_W_alu_result[22] & (H1_d_read # AB1_d_write);


--W1L29 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~58 at LCCOMB_X40_Y17_N8
W1L29 = W1L28 & (!W1_cpu_0_data_master_requests_cfi_flash_0_s1 # !W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 # !W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable);


--W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 at LCFF_X40_Y17_N21
W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 = DFFEAS(W1L68, GLOBAL(A1L16), GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1L142 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_firsttransfer~99 at LCCOMB_X40_Y17_N18
W1L142 = W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 & !H1_i_read & H1_F_pc[20];


--W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] at LCFF_X40_Y17_N23
W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L16), GLOBAL(E1L4),  ,  , W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0],  ,  , VCC);


--W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] at LCFF_X41_Y18_N5
W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEAS(W1L25, GLOBAL(A1L16), GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1L19 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~176 at LCCOMB_X40_Y17_N22
W1L19 = H1_d_read & (W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] # W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1]);


--W1L20 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~177 at LCCOMB_X40_Y17_N26
W1L20 = W1_cpu_0_data_master_requests_cfi_flash_0_s1 & !W1L19 & (!W1L142 # !W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable);


--J1_cpu_0_data_master_dbs_address[0] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[0] at LCFF_X40_Y20_N17
J1_cpu_0_data_master_dbs_address[0] = DFFEAS(J1L8, GLOBAL(A1L16), GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--H1_d_byteenable[3] is DE2_Board:inst|cpu_0:the_cpu_0|d_byteenable[3] at LCFF_X40_Y20_N13
H1_d_byteenable[3] = AMPP_FUNCTION(A1L16, H1L183, E1L4);


--H1_d_byteenable[1] is DE2_Board:inst|cpu_0:the_cpu_0|d_byteenable[1] at LCFF_X40_Y20_N27
H1_d_byteenable[1] = AMPP_FUNCTION(A1L16, H1L181, E1L4);


--J1_cpu_0_data_master_dbs_address[1] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] at LCFF_X40_Y20_N19
J1_cpu_0_data_master_dbs_address[1] = DFFEAS(J1L10, GLOBAL(A1L16), GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1L17 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1~333 at LCCOMB_X40_Y20_N2
W1L17 = J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1] & (H1_d_byteenable[3]) # !J1_cpu_0_data_master_dbs_address[1] & H1_d_byteenable[1]);


--H1_d_byteenable[2] is DE2_Board:inst|cpu_0:the_cpu_0|d_byteenable[2] at LCFF_X40_Y20_N15
H1_d_byteenable[2] = AMPP_FUNCTION(A1L16, H1L182, E1L4);


--H1_d_byteenable[0] is DE2_Board:inst|cpu_0:the_cpu_0|d_byteenable[0] at LCFF_X40_Y20_N23
H1_d_byteenable[0] = AMPP_FUNCTION(A1L16, H1L185, E1L4);


--T1L5 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_byteenable_payload_buffer_s1[0]~60 at LCCOMB_X40_Y20_N30
T1L5 = J1_cpu_0_data_master_dbs_address[1] & (H1_d_byteenable[2]) # !J1_cpu_0_data_master_dbs_address[1] & H1_d_byteenable[0];


--W1L18 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1~334 at LCCOMB_X38_Y19_N0
W1L18 = W1L17 # T1L5 & !J1_cpu_0_data_master_dbs_address[0];


--J1_cpu_0_data_master_no_byte_enables_and_last_term is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_no_byte_enables_and_last_term at LCFF_X41_Y18_N13
J1_cpu_0_data_master_no_byte_enables_and_last_term = DFFEAS(J1L179, GLOBAL(A1L16), GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1L21 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~178 at LCCOMB_X38_Y19_N4
W1L21 = W1L20 & (W1L18 & !J1_cpu_0_data_master_no_byte_enables_and_last_term # !AB1_d_write);


--W1_tri_state_bridge_0_avalon_slave_arb_addend[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0] at LCFF_X40_Y16_N17
W1_tri_state_bridge_0_avalon_slave_arb_addend[0] = DFFEAS(W1L122, GLOBAL(A1L16), GLOBAL(E1L4),  ,  ,  ,  ,  ,  );