de2_board.tan.rpt

Altera FPGA 上利用nios嵌入式处理器实现USB的通信控制

+---------------------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                           ; To                                                                                                                                          ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 3.197 ns                         ; FL_DQ[4]                                                                                                       ; DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[4]           ; --                           ; CLOCK_50                     ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 10.391 ns                        ; delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[0] ; FL_RST_N                                                                                                                                    ; CLOCK_50                     ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 12.166 ns                        ; KEY[0]                                                                                                         ; FL_RST_N                                                                                                                                    ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 0.391 ns                         ; altera_internal_jtag                                                                                           ; DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[7]                                         ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLOCK_50'                     ; N/A   ; None          ; 71.19 MHz ( period = 14.046 ns ) ; DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[18]                                                                ; DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a29~porta_address_reg11 ; CLOCK_50                     ; CLOCK_50                     ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 165.51 MHz ( period = 6.042 ns ) ; DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[0]         ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                ;                                                                                                                                             ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK_50                     ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;