ex6_4_ser_adder.vhd

This is the course for VHDL programming

entity ser_add is
    port(a,b,start,clk:in bit;
        ready:out bit;
        sum8:out bit_vector(7 downto 0));
end ser_add;
architecture beh of ser_add is
    signal shiftreg:bit_vector(7 downto 0);
begin
   process(clk)
      variable bitcount:integer:=0;
      variable sum,co:bit;
   begin
       if start = '1' then --Initialize
            bitcount := 0;co :='0';
            ready <='0'; shiftreg <= "00000000";
       elsif clk'event and clk = '1' then
            if bitcount <8 then--addition loop
            bitcount:= bitcount + 1;
            sum := a xor b xor co;
            co := (a and b) or (b and co) or
                     (co and a);
            shiftreg <=  sum  & shiftreg(7 downto 1);
            elsif bitcount = 8 then ready <= '1';
            end if;
        end if;
    end process;
    sum8 <=  shiftreg;
end beh;
entity ser_add_tb  is 
end ; 
 
architecture ser_add_tb_arch of ser_add_tb is
  signal sum8   :  bit_vector (7 downto 0)  ; 
  signal ready   :  bit  ; 
  signal a   :  bit  ; 
  signal clk   :  bit:='0'  ; 
  signal start   :  bit  ; 
  signal b   :  bit  ; 
  type pattern is array(0 to 3) of
    bit_vector(7 downto 0);
begin
  DUT  : entity work.ser_add  
    port map ( 
      sum8   => sum8  ,
      ready   => ready  ,
      a   => a  ,
      clk   => clk  ,
      	      start   => start  ,
      	     b   => b   ) ; 
      
process
    variable aaa:pattern:=(X"FF",X"77",X"64",X"55");
    variable bbb:pattern:=(X"01",X"ff",X"19",X"AA");
    variable aa:bit_vector (7 downto 0);
    variable bb:bit_vector (7 downto 0);
    	begin
        		clk <= '0';
     		 for i in 0 to 10 loop
      			start <= '1';wait for 100 ps;start <= '0';
      			aa := aaa(i mod 4);bb:= bbb(i mod 4);
         			for j in 0 to 10 loop
         				a <= aa(j mod 8);b<=bb(j mod 8);
        				 wait for 50 ps;clk <= '1';
        				 wait for 50 ps;clk <= '0';
end loop;
     		end loop;
      	        wait;
    	end process;
END ;