ex_p6_18_fill_mem.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 30 行

use std.textio.all;
entity FILL_MEM2 is end FILL_MEM2;
architecture arch of FILL_MEM2 is
	type MEMORY is array(0 to 31)of bit_vector(7 downto 0);
	signal M:memory;
BEGIN
  PROCESS
	VARIABLE lout,lin: line ;
	file DATAFILE:text open READ_MODE is "RAM2.TXT";
	variable b:bit_vector(7 downto 0);
	variable adr:integer;
  begin
	WRITE(lout, string'("Input"),LEFT,10) ;
	WRITE(lout, string'("Data"),LEFT,10) ;
   WRITELINE(OUTPUT, lout) ;
	for i in M'range loop
		if ENDFILE(DATAFILE) then exit;end if;
		readline(DATAFILE,lin);
		read(lin,adr);
		WRITE(lout, adr,LEFT,10);
      WRITELINE(OUTPUT, lout);
      --readline(DATAFILE,lin);
		read(lin,b);
		WRITE(lout, b,LEFT,10) ;
      WRITELINE(OUTPUT, lout) ;
      M(adr) <= b;
	end loop;
	wait;
  END PROCESS;
END arch ;