ex_p6_15_fsm_rand_test.vhd

This is the course for VHDL programming

--FINITE STATE MACHINE TO DETECT 1011 SEQUENCE
package state_def is
   type STATE_TABLE is(RESET,GOT1,GOT10,GOT101);
end state_def;
use work.state_def.all;
entity FSM1011 is
	port(RST,X,CLK :in BIT; Z: out BIT;
	   PORT_STATE,PORT_NEXT_STATE:out STATE_TABLE);
end FSM1011;
architecture DF of FSM1011 is
	
	signal STATE,NEXT_STATE : STATE_TABLE;
begin
	process(CLK,RST,X)
	begin
	if(RST='1')then STATE <= RESET;
	elsif(CLK'event and CLK='1') then
		STATE<=NEXT_STATE;
	end if;
end process;
NEXT_STATE <= RESET   	when STATE=RESET  and X='0' else
		  GOT1    	when STATE=RESET  and X='1' else
		  GOT10   	when STATE=GOT1    and X='0' else
		  GOT1    	when STATE=GOT1    and X='1' else
		  RESET   	when STATE=GOT10  and X='0' else
		  GOT101  	when STATE=GOT10  and X='1' else
		  GOT10   	when STATE=GOT101 and X='0' else
		  GOT1 ;   	-- Default:when STATE=GOT101 and X='1' ;
Z <= '1' when STATE= GOT101 and X='1' else
	'0';
PORT_NEXT_STATE <= NEXT_STATE;
PORT_STATE <= STATE;
end DF;
use work.state_def.all;
entity fsm_rand_tb is end fsm_rand_tb;
architecture BEH of fsm_rand_tb is
    signal RST,X,CLK,Z:BIT;
    signal LFSR:bit_vector(7 downto 0):="11111111";
    signal RESET_RESET,RESET_GOT1,
           GOT1_GOT10,GOT1_GOT1,
           GOT10_RESET,GOT10_GOT101,
           GOT101_GOT10,GOT101_GOT1:integer:=0;
    signal PORT_STATE,PORT_NEXT_STATE:STATE_TABLE;
    shared variable i:integer:=0;
    shared variable run:bit:='1';
begin
    F:entity work.FSM1011(DF)
    port map(RST,X,CLK,Z,PORT_STATE,PORT_NEXT_STATE);
    -- Driving reset and clock
    process
    begin
        RST <= '1';wait for 50 ns;
        RST <= '0';wait for 50 ns;
        while run = '1' loop
           CLK <= '1';wait for 50 ns;
           CLK <= '0';wait for 50 ns;
           i := i+ 1;
        end loop;
        wait;
    end process;
    --Generating LFSR sequence
    process(CLK)
    begin
        if CLK = '1' and CLK'event then
            LFSR <= (LFSR(0) xor LFSR(1)) &
                     LFSR(7 downto 1);
        end if;
    end process;
    X <= LFSR(0);
    --Functional coverage
    process(CLK,PORT_STATE,PORT_NEXT_STATE,X)
    begin
        if CLK = '0' and CLK'event then
           case PORT_STATE is
            when RESET => 
               if X ='0' then
                   RESET_RESET <= RESET_RESET +1;
                   if PORT_NEXT_STATE /= RESET
                   then report "Error at clock no"
                      & integer'image(i) & STATE_TABLE'image(PORT_STATE);
                   end if;
               else
                   RESET_GOT1 <= RESET_GOT1 +1;
                   if PORT_NEXT_STATE /= GOT1
                   then report "Error at clock no"
                      & integer'image(i) & STATE_TABLE'image(PORT_STATE);
                   end if;
                end if;
            when GOT1 => 
               if X ='0' then
                   GOT1_GOT10 <= GOT1_GOT10 +1;
                   if PORT_NEXT_STATE /= GOT10
                   then report "Error at clock no"
                      & integer'image(i) & STATE_TABLE'image(PORT_STATE);
                   end if;
               else
                   GOT1_GOT1 <= GOT1_GOT1 +1;
                   if PORT_NEXT_STATE /= GOT1
                   then report "Error at clock no"
                      & integer'image(i) & STATE_TABLE'image(PORT_STATE);
                   end if;        
               end if;
            when GOT10 => 
               if X ='0' then
                   GOT10_RESET <= GOT10_RESET +1;
                   if PORT_NEXT_STATE /= RESET
                   then report "Error at clock no"
                      & integer'image(i);
                   end if;
               else
                   GOT10_GOT101 <= GOT10_GOT101 +1;
                   if PORT_NEXT_STATE /= GOT101
                   then report "Error at clock no"
                   & integer'image(i);
                   end if;        
               end if;
            when GOT101 => 
               if X ='0' then
                   GOT101_GOT10 <= GOT101_GOT10 +1;
                   if PORT_NEXT_STATE /= GOT10
                   then report "Error at clock no"
                      & integer'image(i);
                   end if;
               else
                   GOT101_GOT1 <= GOT101_GOT1 +1;
                   if PORT_NEXT_STATE /= GOT1
                   then report "Error at clock no"
                   & integer'image(i);
                   end if;        
               end if;
         end case;
         if (RESET_RESET > 25) and (RESET_GOT1 >25) and
            (GOT1_GOT10 > 25) and (GOT1_GOT1 >25) and
            (GOT10_RESET > 25) and (GOT10_GOT101 >25) and
            (GOT101_GOT10 > 25) and (GOT101_GOT1 >25) then
              run := '0';
              report "RESET_RESET=" & integer'image(RESET_RESET);
              report "RESET_GOT1=" & integer'image(RESET_GOT1);
              report "GOT1_GOT10=" & integer'image(GOT1_GOT10);
              report "GOT1_GOT1=" & integer'image(GOT1_GOT1);
              report "GOT10_RESET=" & integer'image(GOT10_RESET);
              report "GOT10_GOT101=" & integer'image(GOT10_GOT101);
              report "GOT101_GOT10=" & integer'image(GOT101_GOT10);
              report "GOT101_GOT1=" & integer'image(GOT101_GOT1);
              report "Test complete";
        end if;      
      end if;
   end process;
end BEH;