ex_p5_29_bcd_8_adder.vhd

This is the course for VHDL programming

package NIBBLE_PACK is
    type NIBBLE_ARRAY is array (7 downto 0) of 
       BIT_VECTOR(3 downto 0);
end NIBBLE_PACK;
package body NIBBLE_PACK is
end NIBBLE_PACK;
use work.NIBBLE_PACK.all;
entity BCD_8_ADDER is 
   port(NA,NB: in NIBBLE_ARRAY;
        Ci : in BIT;
        NS : out NIBBLE_ARRAY;
        co : out BIT);
end BCD_8_ADDER;
architecture struct of BCD_8_ADDER is
   signal c: BIT_VECTOR(8 downto 0);
   component BCD_A is
	   port(x,y:in BIT_VECTOR(3 downto 0);
	     ci:in BIT;
	     sum: out BIT_VECTOR(3 downto 0);
	     co:out BIT);
   end component;
begin
    c(0) <= ci; co <= c(8);
    G:for i in 7 downto 0 generate
    B:BCD_A 
       port map(NA(i),NB(i),
          c(i),NS(i),c(i+1));
    end generate;
end struct;
use work.NIBBLE_PACK.all;
entity BCD_8_ADDER_TB is 
end BCD_8_ADDER_TB;
architecture BEH of BCD_8_ADDER_TB is
    signal A,B,S:NIBBLE_ARRAY;
    signal Ci,co:BIT;
begin
    B1:entity work.BCD_8_ADDER port map(A,B,ci,S,co);
    process
    begin
        for i in 0 to 7 loop
           A(i) <= X"9";
        end loop;
        wait for 100 ns;
        ci <= '1';wait for 100 ns;
        for i in 0 to 7 loop
           A(i) <= X"5";
           B(i) <= X"2";
        end loop;
        wait for 100 ns;
        ci <= '0';wait for 100 ns;
        ci <= '1';wait for 100 ns;
        wait;
    end process;
end BEH;