ex_p5_15_xor_generic.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 25 行

entity nand2 is
   generic(d:time:= 2 ns);	
   port(i1,i2: in BIT ;o : out BIT) ;	
end nand2;
architecture DF of nand2 is
begin
	o<= i1 nand i2 after d;
end DF;
entity xor_generic is
   port( A,B: in BIT; C: out BIT) ;	
end xor_generic;
architecture struct of xor_generic is
    component nand2
       generic(d:time:= 4 ns);
       port (i1,i2: in BIT ; o: out BIT);
    end component;
    signal P,Q,R:bit;
begin
	N1:nand2 port map(A,B,P);
	N2:nand2 port map(A,P,Q);
	N3:nand2 port map(B,P,R);
	N4:nand2 generic map(6ns) port map(Q,R,C);
end STRUCT;