ex_p5_10_combmult_config.vhd

This is the course for VHDL programming

-- 3X3 combinational multiplier
--  BASIC GATES
entity and2 is	port(i1,i2: in BIT ;o : out BIT) ;	end and2;
architecture DF of and2 is
begin
	o<= i1 and i2 after 2 ns;
end DF;
entity xor2 is	port(i1,i2: in BIT ;o : out BIT) ;	end xor2;
architecture DF of xor2 is
begin
	o<= i1 xor i2 after 3 ns;
end DF;
entity OR2 is
	port(i1,i2:in BIT;o:out BIT);
end OR2;
architecture dataflow of OR2 is
begin
	o<= i1 or i2 after 4 ns;
end dataflow;
-- HALF ADDER - DATAFLOW
entity HA is	port(a, b :in BIT; s, c: out BIT);	end HA;
architecture dataflow of HA is
begin
	s<= a xor b;
	c<= a and b;
end dataflow;
-- HALF ADDER - STRUCTURAL
architecture arch_struct of HA is
component and2 port (i1,i2: in BIT ;o : out BIT); end component;
component xor2 port (i1,i2: in BIT ; o: out BIT); end component;
begin
	A1: and2 port map (a, b, c);
	X1: xor2 port map (a, b, s);
end arch_struct;
--STRUCTURAL DESCRIPTION OF FULL ADDER
entity FA is
	port(x,y,ci:in BIT;sum,co:out BIT);
end FA;
architecture struct of FA is
component HA  port(a,b:in BIT;s,c:out BIT);end component;
component OR2 port(i1,i2:in BIT;o:out BIT);end component;
signal s1,c1,c2: BIT;
begin
	HA1:HA  port map(x ,y ,s1  ,c1);
	HA2:HA  port map(s1,ci,sum ,c2);
	ORG:OR2 port map(c1,c2,co);
end struct;

--entity FA is
--	port(a,b,c:in BIT;s,co:out BIT);
--end FA;
architecture DF of FA is
begin
	sum <= x xor y xor ci;
	co <= (x and y) or (x and ci) or (y and ci);
end DF;
use work.all;
entity COMBMULT is
port  (X,Y: in BIT_VECTOR(2 downto 0); 
       Z: out BIT_VECTOR(5 downto 0)); 
end COMBMULT;

architecture STRUCT of COMBMULT is
	type PRODARRAY is array(0 to 2,0 to 2)of BIT;
	signal XY:PRODARRAY;
	signal C00,C01,C10,C11,C20:BIT;
	signal S01,S11:BIT;
	component FA port(a,b,c:in BIT:='0';s,co:out BIT); end component;
begin
	GEN1:for i in 0 to 2 generate
		GEN2:for j in 0 to 2 generate
			GEN3:XY(i,j) <= X(i) and Y(j);
		end generate;
	end generate;
	FA00:FA port map(XY(1,0),open,XY(0,1),Z(1),C00);
	FA01:FA port map(XY(2,0),open,XY(1,1),S01 ,C01);
	FA10:FA port map(S01    ,C00 ,XY(0,2),Z(2),C10);
	FA11:FA port map(XY(2,1),C01 ,XY(1,2),S11 ,C11);
	FA20:FA port map(S11    ,C10 ,OPEN   ,Z(3),C20);
	FA21:FA port map(XY(2,2),C11 ,C20    ,Z(4),Z(5));
	Z(0) <= XY(0,0);
end STRUCT;
configuration config_mult of COMBMULT is
    for STRUCT
       for all:FA use entity work.FA(struct)
         port map(x=>a,y=>b,ci=>c,sum=>s,co=>co);
         for struct
            for all:HA use entity work.HA(arch_struct);
               for arch_struct
                  for all:xor2 use entity work.xor2(DF);end for;
                  for all:and2 use entity work.and2(DF);end for;
               end for;
            end for;
            for all: or2 use entity work.or2(dataflow);end for;
         end for;
       end for;
   end for;
end config_mult;
entity COMBMULT_TB is end COMBMULT_TB;
architecture DF of COMBMULT_TB is
    signal A,B : BIT_VECTOR(2 downto 0);
    signal C   : BIT_VECTOR(5 downto 0);
    component combmult
        port  (X,Y: in BIT_VECTOR(2 downto 0); 
               Z: out BIT_VECTOR(5 downto 0)); 
    end component;
    for M:combmult use configuration work.config_mult;
begin
    M:combmult port map(A,B,C);
    A<="101" after 100 ns,"011" after 400 ns;
    B<="100" after 200 ns,"111" after 300 ns;
end DF;