ex_p5_29_bcd_8_adder_old.vhd

This is the course for VHDL programming

package NIBBLE_PACK is
    type NIBBLE is array(3 downto 0)of BIT;
    type NIBBLE_ARRAY is array (integer range<>) of NIBBLE;
    function conv_NIB_BV(x:NIBBLE) return BIT_VECTOR;
    function conv_BV_NIB(x:BIT_VECTOR) return NIBBLE;
end NIBBLE_PACK;
package body NIBBLE_PACK is 
   function conv_NIB_BV(x:NIBBLE) 
      return BIT_VECTOR is
      variable bv:bit_vector(3 downto 0);
    begin
       for i in 0 to 3 loop
          bv(i) := x(i);
      end loop;
      return bv;
  end conv_NIB_BV;
   function conv_BV_NIB(x:BIT_VECTOR) 
      return NIBBLE is
      variable n:nibble;
    begin
       for i in 0 to 3 loop
          n(i) := x(i);
      end loop;
      return n;
  end conv_BV_NIB;
end NIBBLE_PACK;
use work.NIBBLE_PACK.all;
entity BCD_8_ADDER is 
   port(NA,NB: in NIBBLE_ARRAY(7 downto 0);
        Ci : in BIT;
        NS : out NIBBLE_ARRAY(7 downto 0);
        co : out BIT);
end BCD_8_ADDER;
architecture struct of BCD_8_ADDER is
   signal c: BIT_VECTOR(8 downto 0);
   component BCD_A is
	   port(nib_x,nib_y:in NIBBLE;
	        ci:in BIT;
	        nib_sum: out NIBBLE;
	        co:out BIT);
   end component;
   for all:BCD_A use entity work.BCD_A(struct)
      port map(x  => conv_NIB_BV(nib_x),
               y  => conv_NIB_BV(nib_y),
               ci => ci,
               conv_BV_NIB(sum) => nib_sum,
               co => co);
begin
    c(0) <= ci; co <= c(8);
    G:for i in 0 to 7 generate
    B:BCD_A 
       port map(NA(i),NB(i),c(i),NS(i),c(i+1));
    end generate;
end struct;