ex_p5_16_parity.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor2 is
   generic(d:time := 2 ns);
	port(	i1,i2: in STD_LOGIC; o: out STD_LOGIC);
end xor2;
architecture DF of xor2 is
begin
    o <= i1 xor i2;
end DF;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PAR4 is
     generic(d4:time := 4 ns);
	  port(	A,B,C,D: in STD_LOGIC; P: out STD_LOGIC);
end PAR4;
architecture STRUCT of PAR4 is
   component xor2
       generic(d:time);
       port(	i1,i2: in STD_LOGIC; o: out STD_LOGIC);
   end component;
   signal Q,R,S:STD_LOGIC; 
begin
    X1:xor2 generic map(d4) port map(A,B,R);
    X2:xor2 generic map(d4) port map(C,D,Q);
    X3:xor2 generic map(d4) port map(R,Q,P);
end STRUCT;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PAR16 is
     generic(d16:time := 6 ns);
	  port(	X: in STD_LOGIC_VECTOR(15 downto 0);
	        PARITY: out STD_LOGIC);
end PAR16;
architecture STRUCTURAL of PAR16 is
    component PAR4
       generic(d4:time := 10 ns);
	    port(	A,B,C,D: in STD_LOGIC; P: out STD_LOGIC);
   end component;
   signal Q,R,S,T:STD_LOGIC; 
begin
    P1:PAR4 generic map(d16) port map(X(0),X(1),X(2),X(3),Q);
    P2:PAR4 generic map(d16) port map(X(4),X(5),X(6),X(7),R);
    P3:PAR4 generic map(d16) port map(X(8),X(9),X(10),X(11),S);
    P4:PAR4 generic map(d16) port map(X(0),X(1),X(2),X(3),T);
    P5:PAR4 generic map(d16) port map(Q,R,S,T,PARITY);
end STRUCTURAL;
configuration config_parity of PAR16 is
    for STRUCTURAL
       for all:PAR4 use entity work.PAR4(STRUCT);
          for struct
             for all:xor2 use entity work.xor2(DF);
             end for;
          end for;
       end for;
    end for;
end config_parity;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PAR16_TB is end PAR16_TB;
architecture BEH of PAR16_TB is
    signal D:STD_LOGIC_VECTOR(15 downto 0);
    signal P:STD_LOGIC;
    component PAR16
        generic(d16:time := 6 ns);
	     port(	X: in STD_LOGIC_VECTOR(15 downto 0);
	           PARITY: out STD_LOGIC);
   end component;
    for P16:PAR16 use configuration work.config_parity;
begin
    P16:PAR16 port map(D,P);
    process
    begin
        D<= "0000000000000000";
        for i in 0 to 63 loop
           wait for 100 ns;
           D <= D+1;
       end loop;
       wait;
   end process;
end BEH;