ex_p5_19_fa_nand.vhd

This is the course for VHDL programming

entity OR2 is
	port(i1,i2:in BIT;o:out BIT);
end OR2;
architecture nand_struct of OR2 is
   component nand2
        port(i1,i2: in BIT ;o : out BIT) ;	
   end component;
   signal n1_out,n2_out:bit;
begin
	n1:nand2 port map(i1,i1,n1_out);
	n2:nand2 port map(i2,i2,n2_out);
	n3:nand2 port map(n1_out,n2_out,o);
end nand_struct;

entity and2 is	
   port(i1,i2: in BIT ;o : out BIT) ;	
end and2;
architecture nand_struct of and2 is
   component nand2
        port(i1,i2: in BIT ;o : out BIT) ;	
   end component;
   signal n1_out:bit;
begin
	n1:nand2 port map(i1,i2,n1_out);
	n2:nand2 port map(n1_out,n1_out,o);
end nand_struct;

--entity xor_generic is defined in P5.15(xor from nand)
--entity xor_generic is
--   port( A,B: in BIT; C: out BIT) ;	
--end xor_generic;

entity HA is	
   port(a, b :in BIT; s, c: out BIT);
end HA;
architecture nand_struct of HA is
   component and2 
      port (i1,i2: in BIT ;o : out BIT);
   end component;
   component xor2 
      port( A,B: in BIT; C: out BIT) ; 
   end component;
   for all:and2 use entity work.and2(nand_struct);
   for all:xor2 use entity work.xor_generic;
begin
	A1: and2 port map (a, b, c);
	X1: xor2 port map (a, b, s);
end nand_struct;
entity FA is
	port(x,y,ci:in BIT;sum,co:out BIT);
end FA;

architecture nand_struct of FA is
   component HA
        port(a, b :in BIT; s, c: out BIT);	
   end component;
   component OR2
        port(i1,i2:in BIT;o:out BIT);	
   end component;
   For all: HA use entity WORK.HA (nand_struct);
	For all: OR2 use entity WORK.OR2(nand_struct);
	signal s1,c1,c2:bit;
begin
   HA1:HA  port map(x ,y ,s1  ,c1);
	HA2:HA  port map(s1,ci,sum ,c2);
	ORG:OR2 port map(c1,c2,co);
end nand_struct;