ex_p5_23_tff_cntr.vhd

This is the course for VHDL programming

entity TFF is	
   port(T,CLK,RST: in BIT ;
        Q : out BIT) ;	
end TFF;
architecture DF_DELAY of TFF is
    signal int_Q:bit;
begin
	process(CLK,RST,T)
	begin
	    if RST = '1' then int_Q <= '1';
	    elsif CLK'event and CLK = '0' then
	        if T= '1' then 
	           int_Q <= not int_Q after 5 ns;
	        end if;
	    end if;
	    
	end process;
	Q <= int_Q;
end DF_DELAY;
entity TFF_RIPPLE_CNTR is	
   port(CLK,RST: in BIT ;
        Q : out BIT_VECTOR(2 downto 0)) ;	
end TFF_RIPPLE_CNTR;
architecture struct of TFF_RIPPLE_CNTR is
    signal int_Q:BIT_VECTOR(2 downto 0);
begin
    T0:entity work.TFF(DF_DELAY) 
       port map('1',CLK,RST,int_Q(0));
    T1:entity work.TFF(DF_DELAY) 
       port map('1',int_Q(0),RST,int_Q(1));
    T2:entity work.TFF(DF_DELAY) 
       port map('1',int_Q(1),RST,int_Q(2));
    Q <= int_Q;
end struct;
entity DECODE is
port(ADR : in  BIT_VECTOR(2 downto 0);
     Y: out BIT_VECTOR (7 downto 0));
end DECODE;
Architecture DF of DECODE is
Begin
	Y<=	
	   "00000001" when ADR="000" else
		"00000010" when ADR="001" else
		"00000100" when ADR="010" else
		"00001000" when ADR="011" else
		"00010000" when ADR="100" else
		"00100000" when ADR="101" else
		"01000000" when ADR="110" else
		"10000000" ;
End DF;
entity cntr_decoder is
    port(CLK,RST : in bit;
         Y : out BIT_VECTOR(7 downto 0));
end cntr_decoder;
architecture struct of cntr_decoder is
    signal Q_ADR:BIT_VECTOR(2 downto 0);
    component TFF_RIPPLE_CNTR is	
      port(CLK,RST: in BIT ;
           Q : out BIT_VECTOR(2 downto 0)) ;	
    end component;
    component DECODE is
      port(ADR : in  BIT_VECTOR(2 downto 0);
           Y: out BIT_VECTOR (7 downto 0));
    end component;
begin
    CNTR:TFF_RIPPLE_CNTR port map(CLK,RST,Q_ADR);
    DCDR:DECODE port map(Q_ADR,Y);
end struct;