ex_3_9_2_crc32.vhd

This is the course for VHDL programming

library ieee;
use ieee.std_logic_1164.all;
entity crc is
	port(rst,clk,enable, d : in std_logic;
			crc_out:out std_logic_vector(31 downto 0));
end crc;
architecture a of crc is
	signal lfsr:std_logic_vector(31 downto 0);
	constant poly:std_logic_vector(31 downto 0):= X"04c11db7";
begin
	process(clk,rst,enable,d,lfsr)
		variable ext_inbit:std_logic_vector(31 downto 0);
		variable inbit:std_logic;
	begin
		inbit := d xor lfsr(31);
		for i in 0 to 31 loop
			ext_inbit(i) := inbit;
		end loop;
		if rst = '1' then lfsr <= X"FFFFFFFF";
		elsif clk'event and clk = '1' then
			if enable = '1' then
					lfsr <= (lfsr(30 downto 0) & '0')
					     xor (ext_inbit and poly) ;
			end if;
		end if;
	end process;
	process(lfsr)
	begin
		for i in lfsr'range loop
			crc_out(i) <= not lfsr(lfsr'high -i);
		end loop;
	end process;
end a;