ex_3_7_4_func_proc.vhd

This is the course for VHDL programming

entity testfunc is end testfunc;
architecture beh of testfunc is
   -------------------------------------------
   procedure BYTE_TO_INT(BYTE: in BIT_VECTOR;EQ_INT: out integer) is
      Variable SUM :integer :=0;
   Begin
	   For I in BYTE'range loop
	      If BYTE(I) = '1' then 
	         SUM := SUM + 2**I; end if;
	   End loop;
	   EQ_INT := SUM;
   End BYTE_TO_INT;
   -------------------------------------------
   procedure apply_bits(signal TARGET:out bit;
               STREAM:bit_vector;DELAY:time) is
      begin
	      for i in STREAM'range loop
		      TARGET <= STREAM (i);
		      wait for DELAY;
	         end loop;
   end apply_bits;
-------------------------------------------
function BYTE_TO_INT(BYTE: BIT_VECTOR) return integer is
variable SUM :integer :=0;
begin
	for I in BYTE'range loop
	If BYTE(I) = '1' then SUM:= SUM + 2**I; end if;
	end loop;
	return SUM;
end BYTE_TO_INT;
-------------------------------------------
  function INT_TO_BYTE(x:integer;l:integer)return bit_vector is
		variable b:bit_vector(l-1 downto 0);
		variable y:integer;
	begin
		y:=x;
		for i in b'reverse_range loop
			if (y mod 2) = 1 then b(i) := '1'; end if;
			y := y/2;
		end loop;
		return b;
	end INT_TO_BYTE;
	-------------------------------------------
   function REVERSE(B:bit_vector)return bit_vector is
		variable D:bit_vector(B'reverse_range);
	begin
		for i in B'range loop
			D(i):=B(i);
		end loop;
		return D;
	end REVERSE;
-------------------------------------------
function LOG2 (data_value: integer)	return integer is 
	variable WIDTH	 	: integer := 4; --minimum width
	begin
		for i in 1 to 30 loop
			if (data_value > (2**i)) then   
				WIDTH:= i + 1;
          			end if;          			
      		end loop;
	return WIDTH;
end LOG2;
-------------------------------------------
function make_str_cap(s:string)	return string is 
	variable cap:string(s'range);
begin
    for i in s'range loop
	   if (s(i) >= 'a') and (s(i)<= 'z') then
	   	cap(i):= character'val(character'pos(s(i))-32);
	   else	cap(i) := s(i);
	   end if;
	 end loop;
    return cap;
end make_str_cap;
-------------------------------------------
function bit_to_string(b:bit_vector)      return string is 
	variable s:string(b'low+1 to b'high+1);
begin
   for i in b'range loop
	       if b(b'high-i) = '1' then	
	          s(i+1) := '1';
	       else s(i+1) := '0';
	       end if;
	end loop;
	return s;
end bit_to_string;

-------------------------------------------
function bin_to_gray(b:bit_vector)      
            return bit_vector is 
		variable g:bit_vector(b'range);
begin
   for i in b'range loop
	   if i = b'high then g(i) := b(i);
	   else	g(i) := b(i) xor b(i+1);
	   end if;
	end loop;
	return g;
end bin_to_gray;
-------------------------------------------
  Signal AA:bit_vector(7 downto 0) :="00001111";
  Signal CC:bit_vector(0 to 7) ;
  Signal BB : integer;
  Signal TGT:bit;
-------------------------------------------
  begin
    process
        variable A:bit_vector(7 downto 0) :="00001111";
        variable B : integer;
    begin
       report "BYTE_TO_INT positional";
       BYTE_TO_INT(A,B);
       report "BYTE_TO_INT named";
       BYTE_TO_INT(EQ_INT =>B,BYTE => A);
       report "apply_bits";
       apply_bits(TGT,"11110101",10 ns);
       report "BYTE_TO_INT function";
       BB <= BYTE_TO_INT(A);
       report "INT_TO_BYTE function";
       AA <= INT_TO_BYTE(5,8);
       report "reverse function";
       CC <= reverse(AA);
       report "log(" & integer'image(120) & 
             ")=" & integer'image(LOG2(120));
       report make_str_cap("make capital");
       report bit_to_string("1101");
       report bit_to_string(bin_to_grayquit -sim
       (AA));
       wait;
   end process;
end beh;