ex_p3_9_to_16_func_proc.vhd

This is the course for VHDL programming

--This package contains functions from P3.9 to P3.16
library ieee;
use ieee.std_logic_1164.all;
package functions is
   function PARITY(a:STD_LOGIC_VECTOR) return STD_LOGIC;
   function ONES (L: integer) return BIT_VECTOR;
   type bv_array is array(integer range<>)of bit_vector(3 downto 0);
   procedure apply_vector(signal TARGET: out bit_vector(3 downto 0);
				STREAM:in bv_array;DELAY:in time);
	function COUNT1(a:STD_LOGIC_VECTOR) return integer;
	function IS_XZ(a:STD_LOGIC_VECTOR) 
      		return boolean;
  	Function To_std_ulogic (c:character) return std_ulogic;
  	type LOGIC4 is ('0','1','Z','X');
   type L4_TWO_DIM_ARR is array(LOGIC4,LOGIC4)  of LOGIC4;
   function "or" (a,b:LOGIC4) return LOGIC4;
   procedure COMP(a,b:STD_LOGIC_VECTOR(3  DOWNTO  0);
		signal A_GT_B,A_EQ_B,A_LT_B:out STD_LOGIC);
end functions;

package body functions is
   function PARITY(a:STD_LOGIC_VECTOR) return STD_LOGIC is
		variable temp:std_logic:='0';
   begin
		for i in a'range loop
		temp:=temp xor a(i);
		end loop;
		return temp;
   end PARITY;
   
   function ONES (L: integer) return BIT_VECTOR is
		variable BV : BIT_VECTOR (0 to L-1);
	begin
		for i in BV'range loop
          		BV (i) := '1';        			
      		end loop;
		return BV;
   end ONES;	

   procedure apply_vector(signal TARGET: out bit_vector(3 downto 0);
				STREAM:in bv_array;DELAY:in time) is
	begin
		for i in STREAM'range loop
			TARGET <= STREAM (i);
			wait for DELAY;
		end loop;
	end apply_vector;
	
	function COUNT1(a:STD_LOGIC_VECTOR) return integer is
		variable temp:integer:=0;
   begin
		for i in a'range loop
		if a(i)='1' then temp:=temp +1;end if;
		end loop;
		return temp;
   end COUNT1;

   function IS_XZ(a:STD_LOGIC_VECTOR) 
      		return boolean is
	begin
		for i in a'range loop
		if (a(i)='X') or (a(i)='Z')then
		 return true;end if;
		end loop;
		return false;
   end IS_XZ;
   
   Function To_std_ulogic (c:character) return std_ulogic is
	   Variable u: std_ulogic;
   Begin
	   Case c is
		   When 'U' => u := 'U';
		   When 'X' => u := 'X';
		   When '0' => u := '0';
		   When '1' => u := '1';
		   When 'Z' => u := 'Z';
		   When 'W' => u := 'W';
		   When 'L' => u := 'L';
		   When 'H' => u := 'H';
		   When '-' => u := '-';
		   When others => assert FALSE report "Illegal character";
		                  u:='X';
	   End case;
	   Return u;
   End To_std_ulogic;

   function "or" (a,b:LOGIC4) return LOGIC4 is
      constant or_table: L4_TWO_DIM_ARR:=
  			(('0','1','1','X'),('1','1','1','1'),('1','1','1','1'),('X','1','1','X'));
      begin
		   return or_table(a,b);
      end "or";
   procedure COMP(a,b:STD_LOGIC_VECTOR(3  DOWNTO  0);
		signal A_GT_B,A_EQ_B,A_LT_B:out STD_LOGIC) is
   begin
	   if   (a>b) then A_GT_B<='1'; A_EQ_B<='0'; A_LT_B<='0';
	   elsif(a<b) then A_GT_B<='0'; A_EQ_B<='0'; A_LT_B<='1';
	   else            A_GT_B<='0'; A_EQ_B<='1'; A_LT_B<='0';
	   end if;
   end COMP;


end functions;