ex_3_9_2_mult8.vhd

This is the course for VHDL programming

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MULT8 is
	port(INBUSQ,INBUSM:in std_logic_vector(0 to 7);
		OUTBUSHI, OUTBUSLO: out std_logic_vector(0 to 7);
		CLK, START, RESET: in std_logic;
		DONE :out std_logic);
end MULT8;

architecture RTL of MULT8 is
signal A ,Q , M ,NA, NQ, NM: std_logic_vector(0 to 7);
type int3bit is range 0 to 7;
signal COUNT, NCOUNT : int3bit;
type STATE_TABLE is (INIT, ADD, RSHIFT, TEST, CORRECTION, OVER);
signal STATE,NEXT_STATE : STATE_TABLE;
signal F ,NF : std_logic;

begin
	state_proc:process(CLK, RESET)--Process for updating state 
		begin
			if RESET = '1' then STATE <= INIT;
			elsif(CLK'event and CLK='1')then STATE <= NEXT_STATE;
			end if;
		end process state_proc;
		
	reg_proc:process(CLK, RESET)  -- Process for updating registers
		begin
			if RESET = '1' then 
				A<="00000000";
				Q<="00000000";
				M<="00000000";
				COUNT <= 0;
				F <= '0';
			elsif(CLK'event and CLK='1')then
				A<= NA;
				Q<= NQ;
				M<= NM;
				F<= NF;
				COUNT<=NCOUNT;

			end if;
		end process reg_proc;
	--Next state calculation
	NEXT_STATE <= 	ADD    when STATE=INIT and START = '1' else
			  INIT   	when STATE=INIT and START = '0' else
			  RSHIFT 	when STATE=ADD  else
			  TEST   	when STATE=RSHIFT else
			  CORRECTION when STATE=TEST and COUNT  = 6 else
			  ADD        	when STATE=TEST and COUNT /= 6 else
			  OVER 	when STATE=CORRECTION else
			  INIT 	 	when STATE=OVER else
			  STATE;
	DONE <= '1' when STATE = OVER else '0';
	--Calculate new values of registers
	A_proc:process(STATE,START,Q,A,INBUSQ,INBUSM,F,M,COUNT)
	begin
		if    STATE = INIT and START = '1' then
			NA <= "00000000";
			NQ <= INBUSQ;
			NM <= INBUSM;
			NCOUNT <= 0;
			NF <= '0';
		elsif STATE = ADD and Q(7) = '1' then
			NA <= A + M;
			NQ <= Q;
			NM <= M;
			NF <= (M(0) and Q(7)) or F;
			NCOUNT <= COUNT;
		elsif STATE = RSHIFT  then
			NQ(1 to 7) <= Q(0 to 6); NQ(0)<=A(7);
			NA(1 to 7) <= A(0 to 6); NA(0) <= F;
			NM <= M;
			NF <= F;
			NCOUNT <= COUNT;
		elsif STATE= TEST then
			NA <= A;
			NQ <= Q;
			NF <= F;
			NM <= M;
			NCOUNT<=COUNT + 1 ;
		elsif STATE = CORRECTION and Q(7) = '1' then
			NQ(0 to 6) <= Q(0 to 6);
			NQ(7) <= '0';
			NA <= A - M;
			NM <= M;
			NF <= F;
			NCOUNT <= COUNT;
		elsif STATE = OVER then
			NQ <= Q;
			NA <= A;
			NM <= M;
			NF <= F;
			NCOUNT <= COUNT;
			OUTBUSHI <= A(0) & A(0 to 6);
			OUTBUSLO <= A(7) & Q(0 to 6);
		else NQ<=Q;NA<=A;NF<=F;NM<=M;NCOUNT <= COUNT;	end if;	
	end process A_proc;
end RTL;