shifter.vhd

《CPLD开发实例》的配套光盘文件

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY shifter IS
    PORT ( data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
            shift_left: IN STD_LOGIC;
            shift_right: IN STD_LOGIC;
            clk: IN STD_LOGIC;
            clr : IN STD_LOGIC;
            mode : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
            qout : BUFFER STD_LOGIC_VECTOR (7 DOWNTO 0) );
END shifter;
ARCHITECTURE behave OF shifter IS
  SIGNAL enable: STD_LOGIC;
  BEGIN
  PROCESS 
  BEGIN
   WAIT UNTIL (RISING_EDGE(clk) );    --等待时钟上升沿
    IF (clr = '1') THEN    qout <= "00000000";
     ELSE   CASE mode IS
       WHEN "01" => qout<=shift_right & qout(7 DOWNTO 1);--右移
       WHEN "10" => qout<=qout(6 DOWNTO 0) & shift_left; --左移
         WHEN "11" => qout <= data;                      -- 并行加载
         WHEN OTHERS => NULL;        
        END CASE;
      END IF;
  END PROCESS;
END behave;