ad574_1.vhd

《CPLD开发实例》的配套光盘文件

LIBRARY IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  ENTITY AD574_1 IS
  PORT (D :IN STD_LOGIC_VECTOR(11 DOWNTO 0);  
    CLK ,STATUS  : IN STD_LOGIC;--状态机时钟CLK，AD574状态信号STATUS
          LOCK0   : OUT STD_LOGIC; --内部锁存信号LOCK的测试信号
     CS,A0,RC,K12X8 : OUT STD_LOGIC; --AD574控制信号
      Q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); --锁存数据输出
END AD574_1;
ARCHITECTURE behav OF AD574_1 IS
TYPE states IS (st0, st1, st2, st3,st4);  
  SIGNAL current_state, next_state: states :=st0 ;
  SIGNAL REGL : STD_LOGIC_VECTOR(11 DOWNTO 0);
  SIGNAL LOCK : STD_LOGIC;              
 BEGIN
            K12X8 <= '1';   LOCK0 <= LOCK ;   
COM1: PROCESS(current_state,STATUS)   --决定转换状态的进程
BEGIN                          
  CASE current_state IS           
  WHEN st0 => next_state <= st1;
  WHEN st1 => next_state <= st2;                    
  WHEN st2 => IF (STATUS='1') THEN next_state <= st2; 
                   ELSE    next_state <= st3;                
                END IF ;
  WHEN st3=>      next_state <= st4;     
  WHEN st4=>      next_state <= st0;                                                  
  WHEN OTHERS => next_state <= st0;     
     END CASE ;
       END PROCESS COM1 ;
COM2: PROCESS(current_state)  --输出控制信号的进程
     BEGIN                          
CASE current_state IS           
WHEN st0=> CS<='1'; A0<='1';RC<='1';LOCK<='0'; --初始化 
WHEN st1=> CS<='0'; A0<='0';RC<='0';LOCK<='0'; --启动12位转换                     
WHEN st2=> CS<='0'; A0<='0';RC<='0';LOCK<='0'; --等待转换
WHEN st3=> CS<='0'; A0<='0';RC<='1';LOCK<='0'; --12位并行输出有效     
WHEN st4=>  CS<='0'; A0<='0';RC<='1';LOCK<='1'; -- 锁存数据                                                  
WHEN OTHERS=>CS<='1'; A0<='1';RC<='1';LOCK<='0';--其它情况返回初始态      
END CASE ;
   END PROCESS COM2 ;
   REG: PROCESS (CLK)  -- 时序进程  
    BEGIN
     IF ( CLK'EVENT AND CLK='1')  THEN  current_state <= next_state; 
     END IF;
   END PROCESS REG; 
   LATCH1 : PROCESS (LOCK) -- 数据锁存器进程
        BEGIN
         IF LOCK='1' AND LOCK'EVENT THEN   REGL <= D ;
       END IF;
     END PROCESS ; 
          Q <= REGL;  
END behav;