ad0809.vhd

《CPLD开发实例》的配套光盘文件

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY AD0809 IS
    PORT ( D  : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --0809的8位转换数据输出
                          CLK ,EOC : IN STD_LOGIC; --CLK是转换工作时钟
     LOCK1, ALE, START, OE, ADDA   : OUT STD_LOGIC;
         Q  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)  );
END AD0809;
ARCHITECTURE behav OF AD0809 IS
TYPE states IS (st0, st1, st2, st3,st4,st5,st6) ; --定义各状态子类型
  SIGNAL current_state, next_state: states :=st0 ;
  SIGNAL REGL 	    : STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL LOCK	    : STD_LOGIC; -- 转换后数据输出锁存时钟信号
 BEGIN
    ADDA <= '1'; LOCK1 <=LOCK;
  PRO: PROCESS(current_state,EOC)  BEGIN  --规定各状态转换方式
   CASE current_state IS           
   WHEN st0 => ALE<='0';START<='0';OE<='0';LOCK<='0' ;next_state <= st1;
   WHEN st1 => ALE<='1';START<='0';OE<='0';LOCK<='0' ;next_state <= st2;  
   WHEN st2 => ALE<='0';START<='1';OE<='0';LOCK<='0' ;next_state <= st3;          
   WHEN st3 => ALE<='0';START<='0';OE<='0';LOCK<='0';   
     IF (EOC='1') THEN next_state <= st3;   --测试EOC的下降沿
	  ELSE next_state <= st4;               
     END IF ;
   WHEN st4=> ALE<='0';START<='0';OE<='0';LOCK<='0';   
     IF (EOC='0') THEN next_state <= st4; --测试EOC的上升沿，=1表明转换结束
	  ELSE next_state <= st5;                --继续等待
     END IF ;
   WHEN st5=> ALE<='0';START<='0';OE<='1';LOCK<='0';next_state <= st6;
   WHEN st6=> ALE<='0';START<='0';OE<='1';LOCK<='1';next_state <= st0;                                                  
   WHEN OTHERS => ALE<='0';START<='0';OE<='0';LOCK<='0';next_state <= st0; 
   END CASE ;
 END PROCESS PRO ;
   PROCESS (CLK)  
     BEGIN
       IF ( CLK'EVENT AND CLK='1')  THEN   
          current_state <= next_state; -- 在时钟上升沿，转换至下一状态
       END IF;
   END PROCESS;  -- 由信号current_state将当前状态值带出此进程，进入进程PRO
        PROCESS (LOCK) -- 此进程中，在LOCK的上升沿，将转换好的数据锁入
        BEGIN
        IF LOCK='1' AND LOCK'EVENT THEN   REGL <= D ;
        END IF;
       END PROCESS ; 
            Q <= REGL;
END behav;