x_or1.vhd

来自「《CPLD开发实例》的配套光盘文件」· VHDL 代码 · 共 21 行

---------------二输入或门程序模块（行为级）--------------
library ieee;
use ieee.std_logic_1164.all;
entity x_or1 is
port (
in1 : in bit ;
in2 : in bit ;
out1 : out bit) ;
end x_or1;
architecture behavior of x_or1 is
begin
process(in1, in2)
begin
if in1 = in2 then
out1 <= '0' after 10 ns;
else out1 <= '1' after 10 ns;
end if;
end process;
end behavior;