x_or.vhd

《CPLD开发实例》的配套光盘文件

library ieee;
use ieee.std_logic_1164.all;
entity x_or is
port (
in1 : in bit ;
in2 : in bit ;
out1 : out bit);
end x_or;
architecture rtl of x_or is
begin
out1 <= in1 xor in2 after 10 ns;
end rtl;