myand1.vhd

来自「《CPLD开发实例》的配套光盘文件」· VHDL 代码 · 共 13 行

---------------二输入与门程序模块--------------
library ieee;
use ieee.std_logic_1164.all;
entity myand1 is
port(a,b:in std_logic;
q :out std_logic);
end myand1;
architecture rtl of myand1 is
begin
q<=a and b;
end rtl;