sn74373.vhd

《CPLD开发实例》的配套光盘文件

library ieee;
use ieee.std_logic_1164.all;
entity sn74373 is
port(D:in std_logic_vector(8 downto 1);
     OEN: in std_logic;
     G:in std_logic;
     Q:out std_logic_vector(8 downto 1));
end sn74373;
architecture rtl of sn74373 is
signal sig:std_logic_vector(8 downto 1);
begin
  process(D,OEN,G)
  begin
   if OEN='0' then
     q<=sig;
   else
     q<="ZZZZZZZZ";
   end if;
   if G='1' then
     sig<=D;
   end if;
  end process;
end rtl;