h_adder.vhd

来自「《CPLD开发实例》的配套光盘文件」· VHDL 代码 · 共 13 行

library ieee;
use ieee.std_logic_1164.all; 
entity h_adder IS 
  PORT (a, b : IN STD_LOGIC;  
       co, so : OUT STD_LOGIC);  
end h_adder;     
architecture fh1 OF h_adder  is  
BEGIN   
  so <= NOT(a XOR (NOT b)) ;
  co <= a AND b ;  
END ARCHITECTURE fh1;