f_adder.vhd

来自「《CPLD开发实例》的配套光盘文件」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
 entity f_adder IS
   port (ain,bin,cin  : IN STD_LOGIC;
         cout,sum   : OUT STD_LOGIC );
 end entity f_adder;
 architecture fd1 OF f_adder IS
   COMPONENT h_adder
     PORT (  a,b :  IN STD_LOGIC;
       Co,so :  OUT STD_LOGIC);
   END COMPONENT;
   COMPONENT or2a
      PORT (a,b : IN STD_LOGIC; 
                c : OUT STD_LOGIC);
   end COMPONENT;
SIGNAL d,e,f  :  STD_LOGIC; 
  BEGIN
   u1 : h_adder PORT MAP(a=>ain,b=>bin,
         co=>d,so=>e);    
   u2 : h_adder PORT MAP(a=>e, b=>cin,
         co=>f,so=>sum);
   u3 : or2a PORT MAP(a=>d, b=>f,c=>cout);
 end architecture fd1;