lcd.vhd

CPLD的小程序集合

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lcd is
    Port ( clk : in std_logic;
           Reset : in std_logic;
           lcd_rs : out std_logic;
           lcd_rw : out std_logic;
		 lcd_e  : out std_logic;
   --        data_in : in std_logic_vector(7 downto 0);
   --        char_addr : out std_logic_vector(5 downto 0);
           data : out std_logic_vector(7 downto 0));
end lcd;


architecture Behavioral of lcd is


constant IDLE :         std_logic_vector(10 downto 0) :="00000000000";
constant CLEAR :        std_logic_vector(10 downto 0) :="00000000001";
constant RETURNCURSOR : std_logic_vector(10 downto 0) :="00000000010" ;
constant SETMODE      : std_logic_vector(10 downto 0) :="00000000100";
constant SWITCHMODE   : std_logic_vector(10 downto 0) :="00000001000";
constant SHIFT        : std_logic_vector(10 downto 0) :="00000010000";
constant SETFUNCTION  : std_logic_vector(10 downto 0) :="00000100000";
constant SETCGRAM     : std_logic_vector(10 downto 0) :="00001000000";
constant SETDDRAM     : std_logic_vector(10 downto 0) :="00010000000";
constant READFLAG     : std_logic_vector(10 downto 0) :="00100000000";
constant WRITERAM     : std_logic_vector(10 downto 0) :="01000000000";
constant READRAM      : std_logic_vector(10 downto 0) :="10000000000";




constant cur_inc      : std_logic :='1';
constant cur_dec      : std_logic :='0';
constant cur_shift    : std_logic :='1';
constant cur_noshift  : std_logic :='0';
constant open_display : std_logic :='1';
constant open_cur     : std_logic :='0';
constant blank_cur    : std_logic :='0';
constant shift_display : std_logic :='1';
constant shift_cur    : std_logic :='0';
constant right_shift  : std_logic :='1';
constant left_shift   : std_logic :='0';
constant datawidth8   : std_logic :='1';
constant datawidth4   : std_logic :='0';
constant twoline      : std_logic :='1';
constant oneline      : std_logic :='0';
constant font5x10     : std_logic :='1';
constant font5x7      : std_logic :='0';

signal state : std_logic_vector(10 downto 0);
signal counter : integer range 0 to 127;
signal div_counter : integer range 0 to 15;
signal flag        : std_logic;
constant DIVSS : integer :=15;

signal char_addr : std_logic_vector(5 downto 0);
signal data_in   : std_logic_vector(7 downto 0);
component char_ram
          port( address : in std_logic_vector(5 downto 0) ;
	             data    : out std_logic_vector(7 downto 0)
		         );
end component;


signal clkdiv: std_logic_vector(24 downto 0);

signal clk_int: std_logic;
signal clk_input: std_logic;

component fd
          port(d: in std_logic;
		     clk: in std_logic;
			q  : out std_logic);
end component;
signal sig1,sig2,sig3: std_logic;

begin

process(clk,Reset)
begin
   if(Reset='1')then
     clkdiv<="0000000000000000000000000";
   elsif(clk'event and clk='1')then
     clkdiv<=clkdiv+1;
   end if;
end process;

clk_int<='0'when clkdiv(24 downto 20)="11111"else
         '1';

sig1 <=not sig2;
sig3 <=not clk_int;
clk_input<=sig2;
mydff1:fd port map(d=>sig1,clk=>clk_int,q=>sig2);
mydff2:fd port map(d=>sig2,clk=>sig3,q=>lcd_e);





aa:char_ram
   port map( address=>char_addr,data=>data_in);

   lcd_rs <= '1' when state =WRITERAM or state = READRAM else '0';
	lcd_rw <= '0' when state =CLEAR or state = RETURNCURSOR or state=SETMODE or state=SWITCHMODE or state=SHIFT or state= SETFUNCTION or state=SETCGRAM or state =SETDDRAM or state =WRITERAM else
	          '1';
   data <=      "00000001" when state =CLEAR else
	           "00000010" when state =RETURNCURSOR else
			 "000001"& cur_inc & cur_noshift  when state = SETMODE else
			 "00001" & open_display &open_cur & blank_cur when state =SWITCHMODE else
			 "0001" & shift_display &left_shift &"00" when state = SHIFT else
			 "001" & datawidth8 & twoline &font5x10 & "00" when state=SETFUNCTION else
			 "01000000" when state =SETCGRAM else
			 "10000000" when state =SETDDRAM and counter =0 else
			 "11000000" when state =SETDDRAM and counter /=0 else
			 data_in when state = WRITERAM else
			 "ZZZZZZZZ";

   char_addr    <=conv_std_logic_vector( counter,6) when state =WRITERAM and counter<40 else
	               conv_std_logic_vector( counter-41+8,6) when state= WRITERAM and counter>40 and counter<81-8 else
						conv_std_logic_vector( counter-81+8,6) when state= WRITERAM and counter>81-8 and counter<81 else
						"000000";
  process(clk_input,Reset)
  begin
      if(Reset='1')then 
		   state<=IDLE;
			counter<=0;
			flag<='0';
         div_counter<=0;
      elsif(clk_input'event and clk_input='1')then 
		   case state is
			when IDLE =>
			           if(flag='0')then 
						    state<=SETFUNCTION;
							 flag<='1';
							 counter<=0;
							 div_counter<=0;
                    else
						    if(div_counter<DIVSS )then
							    div_counter<=div_counter +1;
                         state<=IDLE;
                      else
							    div_counter<=0;
								 state <=SHIFT;
                      end if;
                    end if;
         when CLEAR    =>
			           state<=SETMODE;
         when SETMODE  =>
			           state<=WRITERAM;
         when RETURNCURSOR =>
			           state<=WRITERAM;
         when SWITCHMODE =>
			           state<=CLEAR;
         when SHIFT      =>
			           state<=IDLE;
         when SETFUNCTION =>
			           state<=SWITCHMODE;
         when SETCGRAM   =>
			           state<=IDLE;
         when SETDDRAM   =>
			           state<=WRITERAM;
         when READFLAG   =>
			           state<=IDLE;
         when WRITERAM   =>
			           if(counter =40)then 
						    state<=SETDDRAM;
							 counter<=counter+1;
                    elsif(counter/=40 and counter<81)then
						    state<=WRITERAM;
							 counter<=counter+1;
                    else
						    state<=SHIFT;
                    end if;
         when READRAM =>
			           state<=IDLE;
         when others  =>
			           state<=IDLE;
         end case;
    end if;
  end process;

  
end Behavioral;