📄 lcd.rpt
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data_I(0) <= ((_14_.EXP)
OR (EXP19_.EXP)
OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND
counter(3) AND counter(0) AND NOT counter(4) AND NOT counter(1) AND
NOT counter(5))
OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND
counter(3) AND counter(0) AND NOT counter(4) AND counter(2) AND
counter(5))
OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND
NOT counter(3) AND counter(0) AND counter(1) AND NOT counter(5) AND
NOT counter(6))
OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND
NOT counter(3) AND NOT counter(0) AND counter(4) AND NOT counter(2) AND
NOT counter(5)));
data(0) <= data_I(0) when data_OE(0) = '1' else 'Z';
data_OE(0) <= NOT ((NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3));
data_I(3) <= ((state_FFT1.EXP)
OR (EXP17_.EXP)
OR (state_FFT1 AND NOT state_FFT3 AND counter(3) AND
counter(0) AND NOT counter(4) AND counter(1) AND NOT counter(5) AND
counter(6))
OR (state_FFT1 AND NOT state_FFT3 AND counter(3) AND
NOT counter(4) AND counter(1) AND counter(2) AND NOT counter(5) AND
counter(6))
OR (state_FFT1 AND NOT state_FFT3 AND NOT counter(3) AND
NOT counter(0) AND counter(4) AND counter(2) AND counter(5) AND
NOT counter(6))
OR (state_FFT1 AND NOT state_FFT3 AND NOT counter(3) AND
counter(0) AND counter(4) AND counter(1) AND NOT counter(2) AND
NOT counter(5) AND NOT counter(6)));
data(3) <= data_I(3) when data_OE(3) = '1' else 'Z';
data_OE(3) <= NOT ((NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3));
data_I(7) <= (NOT state_FFT1 AND state_FFT2 AND NOT state_FFT3);
data(7) <= data_I(7) when data_OE(7) = '1' else 'Z';
data_OE(7) <= NOT ((NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3));
FDCPE_div_counter0: FDCPE port map (div_counter(0),div_counter_D(0),div_counter_C(0),Reset,'0',div_counter_CE(0));
div_counter_D(0) <= (NOT div_counter(0) AND flag);
div_counter_C(0) <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND
clkdiv(23) AND clkdiv(24)));
div_counter_CE(0) <= (NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3);
FDCPE_div_counter1: FDCPE port map (div_counter(1),div_counter_D(1),div_counter_C(1),Reset,'0',div_counter_CE(1));
div_counter_D(1) <= ((div_counter(0) AND NOT div_counter(1) AND flag)
OR (NOT div_counter(0) AND div_counter(1) AND flag));
div_counter_C(1) <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND
clkdiv(23) AND clkdiv(24)));
div_counter_CE(1) <= (NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3);
FTCPE_div_counter2: FTCPE port map (div_counter(2),div_counter_T(2),div_counter_C(2),Reset,'0',div_counter_CE(2));
div_counter_T(2) <= ((div_counter(2) AND NOT flag)
OR (div_counter(0) AND div_counter(1) AND flag));
div_counter_C(2) <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND
clkdiv(23) AND clkdiv(24)));
div_counter_CE(2) <= (NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3);
FTCPE_div_counter3: FTCPE port map (div_counter(3),div_counter_T(3),div_counter_C(3),Reset,'0',div_counter_CE(3));
div_counter_T(3) <= ((div_counter(3) AND NOT flag)
OR (div_counter(0) AND div_counter(1) AND div_counter(2) AND
flag));
div_counter_C(3) <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND
clkdiv(23) AND clkdiv(24)));
div_counter_CE(3) <= (NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3);
FDCPE_flag: FDCPE port map (flag,'1',flag_C,Reset,'0',flag_CE);
flag_C <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND
clkdiv(23) AND clkdiv(24)));
flag_CE <= (NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3 AND NOT flag);
lcd_rs <= (state_FFT1 AND state_FFT2 AND NOT state_FFT3);
lcd_rw <= (NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3);
FTCPE_state_FFT1: FTCPE port map (state_FFT1,state_FFT1_T,state_FFT1_C,Reset,'0');
state_FFT1_T <= ((_11_.EXP)
OR (NOT state_FFT1 AND state_FFT2)
OR (NOT state_FFT1 AND state_FFT3));
state_FFT1_C <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND
clkdiv(23) AND clkdiv(24)));
FDCPE_state_FFT2: FDCPE port map (state_FFT2,state_FFT2_D,state_FFT2_C,Reset,'0');
state_FFT2_D <= ((data_7_OBUFE.EXP)
OR (_10_.EXP)
OR (state_FFT1 AND state_FFT3)
OR (NOT state_FFT1 AND state_FFT2)
OR (state_FFT2 AND NOT counter(6)));
state_FFT2_C <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND
clkdiv(23) AND clkdiv(24)));
FTCPE_state_FFT3: FTCPE port map (state_FFT3,state_FFT3_T,state_FFT3_C,Reset,'0');
state_FFT3_T <= ((state_FFT1 AND state_FFT2 AND state_FFT3)
OR (NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3 AND NOT flag));
state_FFT3_C <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND
clkdiv(23) AND clkdiv(24)));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
**************************** Device Pin Out ****************************
Device : XC95144XL-10-TQ144
Pin Signal Pin Signal
No. Name No. Name
1 VCC 73 VCC
2 TIE 74 TIE
3 TIE 75 data<0>
4 TIE 76 TIE
5 TIE 77 TIE
6 TIE 78 TIE
7 TIE 79 TIE
8 VCC 80 TIE
9 TIE 81 TIE
10 TIE 82 TIE
11 TIE 83 TIE
12 TIE 84 VCC
13 TIE 85 TIE
14 TIE 86 TIE
15 TIE 87 TIE
16 TIE 88 TIE
17 TIE 89 GND
18 GND 90 GND
19 TIE 91 TIE
20 TIE 92 TIE
21 TIE 93 TIE
22 TIE 94 TIE
23 TIE 95 TIE
24 TIE 96 TIE
25 TIE 97 TIE
26 TIE 98 TIE
27 TIE 99 GND
28 TIE 100 TIE
29 GND 101 TIE
30 TIE 102 TIE
31 TIE 103 TIE
32 TIE 104 TIE
33 TIE 105 TIE
34 TIE 106 TIE
35 TIE 107 TIE
36 GND 108 GND
37 VCC 109 VCC
38 TIE 110 Reset
39 TIE 111 TIE
40 TIE 112 TIE
41 TIE 113 TIE
42 VCC 114 GND
43 TIE 115 TIE
44 TIE 116 TIE
45 TIE 117 TIE
46 TIE 118 TIE
47 GND 119 TIE
48 TIE 120 TIE
49 TIE 121 TIE
50 TIE 122 TDO
51 TIE 123 GND
52 TIE 124 TIE
53 TIE 125 TIE
54 TIE 126 TIE
55 VCC 127 VCC
56 lcd_rw 128 clk
57 lcd_rs 129 TIE
58 data<7> 130 TIE
59 TIE 131 TIE
60 TIE 132 TIE
61 data<6> 133 TIE
62 GND 134 TIE
63 TDI 135 TIE
64 data<4> 136 TIE
65 TMS 137 TIE
66 data<5> 138 TIE
67 TCK 139 TIE
68 TIE 140 TIE
69 data<3> 141 VCC
70 data<1> 142 TIE
71 data<2> 143 TIE
72 GND 144 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-10-TQ144
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Set Unused I/O Pin Termination : FLOAT
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25
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