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📄 lcd.rpt

📁 CPLD的小程序集合
💻 RPT
📖 第 1 页 / 共 5 页
字号:
(unused)              0       0     0   5     FB6_4         111   I/O     
(unused)              0       0     0   5     FB6_5         110   I/O     I
(unused)              0       0     0   5     FB6_6         112   I/O     
(unused)              0       0     0   5     FB6_7               (b)     
(unused)              0       0     0   5     FB6_8         113   I/O     
(unused)              0       0     0   5     FB6_9         116   I/O     
(unused)              0       0     0   5     FB6_10        115   I/O     
(unused)              0       0     0   5     FB6_11        119   I/O     
(unused)              0       0     0   5     FB6_12        120   I/O     
(unused)              0       0     0   5     FB6_13              (b)     
(unused)              0       0     0   5     FB6_14        121   I/O     
(unused)              0       0     0   5     FB6_15        124   I/O     
(unused)              0       0     0   5     FB6_16        117   I/O     
(unused)              0       0     0   5     FB6_17        125   I/O     
(unused)              0       0     0   5     FB6_18              (b)     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB7 ***********************************
Number of function block inputs used/remaining:               19/35
Number of signals used by logic mapping into function block:  19
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0   /\3   2     FB7_1               (b)     (b)
data<2>               2       0   \/3   0     FB7_2   STD   71    I/O     O
data<0>              17      12<-   0   0     FB7_3   STD   75    I/O     O
(unused)              0       0   /\5   0     FB7_4               (b)     (b)
(unused)              0       0   /\4   1     FB7_5         74    I/O     (b)
div_counter<0>        4       0   \/1   0     FB7_6   STD   76    I/O     (b)
(unused)              0       0   \/5   0     FB7_7         77    I/O     (b)
data<4>_BUFR         16      11<-   0   0     FB7_8   STD   78    I/O     (b)
(unused)              0       0   /\5   0     FB7_9         80    I/O     (b)
(unused)              0       0   \/4   1     FB7_10        79    I/O     (b)
(unused)              0       0   \/5   0     FB7_11        82    I/O     (b)
(unused)              0       0   \/5   0     FB7_12        85    I/O     (b)
data<2>_BUFR         16      14<- \/3   0     FB7_13  STD   81    I/O     (b)
(unused)              0       0   \/5   0     FB7_14        86    I/O     (b)
data<1>_BUFR         18      13<-   0   0     FB7_15  STD   87    I/O     (b)
(unused)              0       0   /\5   0     FB7_16        83    I/O     (b)
(unused)              0       0   \/5   0     FB7_17        88    I/O     (b)
data<6>_BUFR         13       8<-   0   0     FB7_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: Reset              8: counter<1>        14: data<2>_BUFR 
  2: clkdiv<20>         9: counter<2>        15: div_counter<0> 
  3: clkdiv<21>        10: counter<3>        16: flag 
  4: clkdiv<22>        11: counter<4>        17: state_FFT1 
  5: clkdiv<23>        12: counter<5>        18: state_FFT2 
  6: clkdiv<24>        13: counter<6>        19: state_FFT3 
  7: counter<0>       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
data<2>              .............X..XXX..................... 4       4
data<0>              ......XXXXXXX...XXX..................... 10      10
div_counter<0>       XXXXXX........XXXXX..................... 11      11
data<4>_BUFR         ......XXXXXXX...XXX..................... 10      10
data<2>_BUFR         ......XXXXXXX...XXX..................... 10      10
data<1>_BUFR         ......XXXXXXX...XXX..................... 10      10
data<6>_BUFR         ......XXXXXXX...XXX..................... 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB8 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB8_1               (b)     
(unused)              0       0     0   5     FB8_2         91    I/O     
(unused)              0       0     0   5     FB8_3         95    I/O     
(unused)              0       0     0   5     FB8_4         97    I/O     
(unused)              0       0     0   5     FB8_5         92    I/O     
(unused)              0       0     0   5     FB8_6         93    I/O     
(unused)              0       0     0   5     FB8_7               (b)     
(unused)              0       0     0   5     FB8_8         94    I/O     
(unused)              0       0     0   5     FB8_9         96    I/O     
(unused)              0       0     0   5     FB8_10        101   I/O     
(unused)              0       0     0   5     FB8_11        98    I/O     
(unused)              0       0     0   5     FB8_12        100   I/O     
(unused)              0       0     0   5     FB8_13        103   I/O     
(unused)              0       0     0   5     FB8_14        102   I/O     
(unused)              0       0     0   5     FB8_15        104   I/O     
(unused)              0       0     0   5     FB8_16        107   I/O     
(unused)              0       0     0   5     FB8_17        105   I/O     
(unused)              0       0     0   5     FB8_18              (b)     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.






























data_I(1) <= data(1)_BUFR;
data(1) <= data_I(1) when data_OE(1) = '1' else 'Z';
data_OE(1) <= NOT ((NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3));


data_I(4) <= data(4)_BUFR;
data(4) <= data_I(4) when data_OE(4) = '1' else 'Z';
data_OE(4) <= NOT ((NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3));


data_I(5) <= data(5)_BUFR;
data(5) <= data_I(5) when data_OE(5) = '1' else 'Z';
data_OE(5) <= NOT ((NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3));


data_I(6) <= data(6)_BUFR;
data(6) <= data_I(6) when data_OE(6) = '1' else 'Z';
data_OE(6) <= NOT ((NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3));


data_I(2) <= data(2)_BUFR;
data(2) <= data_I(2) when data_OE(2) = '1' else 'Z';
data_OE(2) <= NOT ((NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3));

FTCPE_clkdiv0: FTCPE port map (clkdiv(0),'1',clk,Reset,'0');

FTCPE_clkdiv10: FTCPE port map (clkdiv(10),clkdiv_T(10),clk,Reset,'0');
clkdiv_T(10) <= (clkdiv(0) AND clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND 
	clkdiv(4) AND clkdiv(5) AND clkdiv(6) AND clkdiv(7) AND clkdiv(8) AND 
	clkdiv(9));

FTCPE_clkdiv11: FTCPE port map (clkdiv(11),clkdiv_T(11),clk,Reset,'0');
clkdiv_T(11) <= (clkdiv(0) AND clkdiv(10) AND clkdiv(1) AND clkdiv(2) AND 
	clkdiv(3) AND clkdiv(4) AND clkdiv(5) AND clkdiv(6) AND clkdiv(7) AND 
	clkdiv(8) AND clkdiv(9));

FTCPE_clkdiv12: FTCPE port map (clkdiv(12),clkdiv_T(12),clk,Reset,'0');
clkdiv_T(12) <= (clkdiv(0) AND clkdiv(10) AND clkdiv(11) AND clkdiv(1) AND 
	clkdiv(2) AND clkdiv(3) AND clkdiv(4) AND clkdiv(5) AND clkdiv(6) AND 
	clkdiv(7) AND clkdiv(8) AND clkdiv(9));

FTCPE_clkdiv13: FTCPE port map (clkdiv(13),clkdiv_T(13),clk,Reset,'0');
clkdiv_T(13) <= (clkdiv(0) AND clkdiv(10) AND clkdiv(11) AND 
	clkdiv(12) AND clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND clkdiv(4) AND 
	clkdiv(5) AND clkdiv(6) AND clkdiv(7) AND clkdiv(8) AND clkdiv(9));

FTCPE_clkdiv14: FTCPE port map (clkdiv(14),clkdiv_T(14),clk,Reset,'0');
clkdiv_T(14) <= (clkdiv(0) AND clkdiv(10) AND clkdiv(11) AND 
	clkdiv(12) AND clkdiv(13) AND clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND 
	clkdiv(4) AND clkdiv(5) AND clkdiv(6) AND clkdiv(7) AND clkdiv(8) AND 
	clkdiv(9));

FTCPE_clkdiv15: FTCPE port map (clkdiv(15),clkdiv_T(15),clk,Reset,'0');
clkdiv_T(15) <= (clkdiv(0) AND clkdiv(10) AND clkdiv(11) AND 
	clkdiv(12) AND clkdiv(13) AND clkdiv(14) AND clkdiv(1) AND clkdiv(2) AND 
	clkdiv(3) AND clkdiv(4) AND clkdiv(5) AND clkdiv(6) AND clkdiv(7) AND 
	clkdiv(8) AND clkdiv(9));

FTCPE_clkdiv16: FTCPE port map (clkdiv(16),clkdiv_T(16),clk,Reset,'0');
clkdiv_T(16) <= (clkdiv(0) AND clkdiv(10) AND clkdiv(11) AND 
	clkdiv(12) AND clkdiv(13) AND clkdiv(14) AND clkdiv(15) AND 
	clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND clkdiv(4) AND clkdiv(5) AND 
	clkdiv(6) AND clkdiv(7) AND clkdiv(8) AND clkdiv(9));

FTCPE_clkdiv17: FTCPE port map (clkdiv(17),clkdiv_T(17),clk,Reset,'0');
clkdiv_T(17) <= (clkdiv(0) AND clkdiv(10) AND clkdiv(11) AND 
	clkdiv(12) AND clkdiv(13) AND clkdiv(14) AND clkdiv(15) AND 
	clkdiv(16) AND clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND clkdiv(4) AND 

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