📄 lcd.rpt
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cpldfit: version G.28 Xilinx Inc.
Fitter Report
Design Name: lcd Date: 4- 5-2005, 4:12PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
55 /144 ( 38%) 268 /720 ( 37%) 40 /144 ( 28%) 12 /117 ( 10%) 104/432 ( 24%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 2 2 | I/O : 12 97
Output : 10 10 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 12 12
MACROCELL RESOURCES:
Total Macrocells Available 144
Registered Macrocells 40
Non-registered Macrocell driving I/O 10
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 55 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 55 macrocells used (MC).
End of Resource Summary
**************************** Errors and Warnings *************************
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB5,
because too many function block product terms are required. Buffering output
signal data<1> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB5,
because too many function block product terms are required. Buffering output
signal data<4> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB5,
because too many function block product terms are required. Buffering output
signal data<5> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB5,
because too many function block product terms are required. Buffering output
signal data<6> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB7,
because too many function block product terms are required. Buffering output
signal data<2> to allow all signals assigned to this function block to be
placed.
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
clkdiv<0> 2 2 FB2_8 STD 5 GTS/I/O (b) RESET
clkdiv<10> 3 12 FB1_18 STD (b) (b) RESET
clkdiv<11> 3 13 FB1_17 STD 30 GCK/I/O (b) RESET
clkdiv<12> 3 14 FB1_16 STD 35 I/O (b) RESET
clkdiv<13> 3 15 FB1_15 STD 28 I/O (b) RESET
clkdiv<14> 3 16 FB1_14 STD 27 I/O (b) RESET
clkdiv<15> 3 17 FB1_13 STD (b) (b) RESET
clkdiv<16> 3 18 FB1_12 STD 26 I/O (b) RESET
clkdiv<17> 3 19 FB1_11 STD 24 I/O (b) RESET
clkdiv<18> 3 20 FB1_10 STD 31 I/O (b) RESET
clkdiv<19> 3 21 FB1_9 STD 22 I/O (b) RESET
clkdiv<1> 3 3 FB2_13 STD 12 I/O (b) RESET
clkdiv<20> 3 22 FB1_8 STD 21 I/O (b) RESET
clkdiv<21> 3 23 FB1_7 STD (b) (b) RESET
clkdiv<22> 3 24 FB1_6 STD 20 I/O (b) RESET
clkdiv<23> 3 25 FB1_5 STD 19 I/O (b) RESET
clkdiv<24> 3 26 FB1_4 STD 25 I/O (b) RESET
clkdiv<2> 3 4 FB2_12 STD 10 I/O (b) RESET
clkdiv<3> 3 5 FB2_11 STD 9 I/O (b) RESET
clkdiv<4> 3 6 FB2_10 STD 7 I/O (b) RESET
clkdiv<5> 3 7 FB3_18 STD (b) (b) RESET
clkdiv<6> 3 8 FB3_17 STD 51 I/O (b) RESET
clkdiv<7> 3 9 FB1_3 STD 17 I/O (b) RESET
clkdiv<8> 3 10 FB1_2 STD 16 I/O (b) RESET
clkdiv<9> 3 11 FB1_1 STD 23 I/O (b) RESET
counter<0> 6 17 FB5_10 STD 68 I/O (b) RESET
counter<1> 5 15 FB5_6 STD 54 I/O (b) RESET
counter<2> 5 16 FB5_5 STD 53 I/O (b) RESET
counter<3> 5 17 FB5_4 STD (b) (b) RESET
counter<4> 5 17 FB5_3 STD 59 I/O (b) RESET
counter<5> 4 17 FB5_2 STD 52 I/O (b) RESET
counter<6> 4 17 FB5_1 STD (b) (b) RESET
data<0> 17 10 FB7_3 STD FAST 75 I/O O
data<1> 2 4 FB5_13 STD FAST 70 I/O O
data<1>_BUFR 18 10 FB7_15 STD 87 I/O (b)
data<2> 2 4 FB7_2 STD FAST 71 I/O O
data<2>_BUFR 16 10 FB7_13 STD 81 I/O (b)
data<3> 11 10 FB5_17 STD FAST 69 I/O O
data<4> 2 4 FB5_15 STD FAST 64 I/O O
data<4>_BUFR 16 10 FB7_8 STD 78 I/O (b)
data<5> 2 4 FB5_7 STD FAST 66 I/O O
data<5>_BUFR 15 10 FB2_1 STD 142 I/O (b)
data<6> 2 4 FB5_14 STD FAST 61 I/O O
data<6>_BUFR 13 10 FB7_18 STD (b) (b)
data<7> 2 3 FB5_11 STD FAST 58 I/O O
div_counter<0> 4 11 FB7_6 STD 76 I/O (b) RESET
div_counter<1> 5 12 FB2_17 STD 15 I/O (b) RESET
div_counter<2> 5 13 FB2_16 STD 14 I/O (b) RESET
div_counter<3> 5 14 FB2_15 STD 13 I/O (b) RESET
flag 3 10 FB2_9 STD 6 GTS/I/O (b) RESET
lcd_rs 1 3 FB5_9 STD FAST 57 I/O O
lcd_rw 1 3 FB5_8 STD FAST 56 I/O O
state_FFT1 7 21 FB5_16 STD (b) (b) RESET
state_FFT2 7 16 FB5_12 STD 60 I/O (b) RESET
state_FFT3 4 10 FB2_14 STD 11 I/O (b) RESET
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
Reset FB6_5 110 I/O I
clk FB4_5 128 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 18 26 26 54 0/0 15
FB2 11 26 26 51 0/0 15
FB3 2 8 8 6 0/0 15
FB4 0 0 0 0 0/0 15
FB5 17 25 25 71 8/0 14
FB6 0 0 0 0 0/0 13
FB7 7 19 19 86 2/0 15
FB8 0 0 0 0 0/0 15
---- ----- ----- -----
55 268 10/0 117
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
clkdiv<9> 3 0 0 2 FB1_1 STD 23 I/O (b)
clkdiv<8> 3 0 0 2 FB1_2 STD 16 I/O (b)
clkdiv<7> 3 0 0 2 FB1_3 STD 17 I/O (b)
clkdiv<24> 3 0 0 2 FB1_4 STD 25 I/O (b)
clkdiv<23> 3 0 0 2 FB1_5 STD 19 I/O (b)
clkdiv<22> 3 0 0 2 FB1_6 STD 20 I/O (b)
clkdiv<21> 3 0 0 2 FB1_7 STD (b) (b)
clkdiv<20> 3 0 0 2 FB1_8 STD 21 I/O (b)
clkdiv<19> 3 0 0 2 FB1_9 STD 22 I/O (b)
clkdiv<18> 3 0 0 2 FB1_10 STD 31 I/O (b)
clkdiv<17> 3 0 0 2 FB1_11 STD 24 I/O (b)
clkdiv<16> 3 0 0 2 FB1_12 STD 26 I/O (b)
clkdiv<15> 3 0 0 2 FB1_13 STD (b) (b)
clkdiv<14> 3 0 0 2 FB1_14 STD 27 I/O (b)
clkdiv<13> 3 0 0 2 FB1_15 STD 28 I/O (b)
clkdiv<12> 3 0 0 2 FB1_16 STD 35 I/O (b)
clkdiv<11> 3 0 0 2 FB1_17 STD 30 GCK/I/O (b)
clkdiv<10> 3 0 0 2 FB1_18 STD (b) (b)
Signals Used by Logic in Function Block
1: Reset 10: clkdiv<16> 19: clkdiv<2>
2: clk 11: clkdiv<17> 20: clkdiv<3>
3: clkdiv<0> 12: clkdiv<18> 21: clkdiv<4>
4: clkdiv<10> 13: clkdiv<19> 22: clkdiv<5>
5: clkdiv<11> 14: clkdiv<1> 23: clkdiv<6>
6: clkdiv<12> 15: clkdiv<20> 24: clkdiv<7>
7: clkdiv<13> 16: clkdiv<21> 25: clkdiv<8>
8: clkdiv<14> 17: clkdiv<22> 26: clkdiv<9>
9: clkdiv<15> 18: clkdiv<23>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
clkdiv<9> XXX..........X....XXXXXXX............... 11 11
clkdiv<8> XXX..........X....XXXXXX................ 10 10
clkdiv<7> XXX..........X....XXXXX................. 9 9
clkdiv<24> XXXXXXXXXXXXXXXXXXXXXXXXXX.............. 26 26
clkdiv<23> XXXXXXXXXXXXXXXXX.XXXXXXXX.............. 25 25
clkdiv<22> XXXXXXXXXXXXXXXX..XXXXXXXX.............. 24 24
clkdiv<21> XXXXXXXXXXXXXXX...XXXXXXXX.............. 23 23
clkdiv<20> XXXXXXXXXXXXXX....XXXXXXXX.............. 22 22
clkdiv<19> XXXXXXXXXXXX.X....XXXXXXXX.............. 21 21
clkdiv<18> XXXXXXXXXXX..X....XXXXXXXX.............. 20 20
clkdiv<17> XXXXXXXXXX...X....XXXXXXXX.............. 19 19
clkdiv<16> XXXXXXXXX....X....XXXXXXXX.............. 18 18
clkdiv<15> XXXXXXXX.....X....XXXXXXXX.............. 17 17
clkdiv<14> XXXXXXX......X....XXXXXXXX.............. 16 16
clkdiv<13> XXXXXX.......X....XXXXXXXX.............. 15 15
clkdiv<12> XXXXX........X....XXXXXXXX.............. 14 14
clkdiv<11> XXXX.........X....XXXXXXXX.............. 13 13
clkdiv<10> XXX..........X....XXXXXXXX.............. 12 12
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
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