lcd.syr

CPLD的小程序集合

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: lcd.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : lcd.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : lcd
Output Format                      : NGC
Target Device                      : xc9500xl

---- Source Options
Top Module Name                    : lcd
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : lcd.lso
verilog2001                        : YES
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/LCD is now defined in a different file: was H:/CindyWang/mars/cpld/lcd/lcd/lcd.vhd, now is E:/Cindy/DevelopBoard/Mars-7128/        /VHDL/lcd/lcd/lcd.vhd
WARNING:HDLParsers:3215 - Unit work/LCD/BEHAVIORAL is now defined in a different file: was H:/CindyWang/mars/cpld/lcd/lcd/lcd.vhd, now is E:/Cindy/DevelopBoard/Mars-7128/        /VHDL/lcd/lcd/lcd.vhd
WARNING:HDLParsers:3215 - Unit work/CHAR_RAM is now defined in a different file: was H:/CindyWang/mars/cpld/lcd/lcd/lcd1602.vhdl, now is E:/Cindy/DevelopBoard/Mars-7128/        /VHDL/lcd/lcd/lcd1602.vhdl
WARNING:HDLParsers:3215 - Unit work/CHAR_RAM/FUN is now defined in a different file: was H:/CindyWang/mars/cpld/lcd/lcd/lcd1602.vhdl, now is E:/Cindy/DevelopBoard/Mars-7128/        /VHDL/lcd/lcd/lcd1602.vhdl
Compiling vhdl file E:/Cindy/DevelopBoard/Mars-7128/        /VHDL/lcd/lcd/lcd1602.vhdl in Library work.
Architecture fun of Entity char_ram is up to date.
Compiling vhdl file E:/Cindy/DevelopBoard/Mars-7128/        /VHDL/lcd/lcd/lcd.vhd in Library work.
Entity <lcd> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <lcd> (Architecture <behavioral>).
WARNING:Xst:766 - E:/Cindy/DevelopBoard/Mars-7128/        /VHDL/lcd/lcd/lcd.vhd line 105: Generating a Black Box for component <fd>.
WARNING:Xst:766 - E:/Cindy/DevelopBoard/Mars-7128/        /VHDL/lcd/lcd/lcd.vhd line 106: Generating a Black Box for component <fd>.
Entity <lcd> analyzed. Unit <lcd> generated.

Analyzing Entity <char_ram> (Architecture <fun>).
Entity <char_ram> analyzed. Unit <char_ram> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <char_ram>.
    Related source file is E:/Cindy/DevelopBoard/Mars-7128/        /VHDL/lcd/lcd/lcd1602.vhdl.
    Found 32x8-bit ROM for signal <$n0000>.
    Summary:
	inferred   1 ROM(s).
Unit <char_ram> synthesized.


Synthesizing Unit <lcd>.
    Related source file is E:/Cindy/DevelopBoard/Mars-7128/        /VHDL/lcd/lcd/lcd.vhd.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 12                                             |
    | Inputs             | 4                                              |
    | Outputs            | 9                                              |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |
    -----------------------------------------------------------------------
    Found 8-bit tristate buffer for signal <data>.
    Found 4-bit comparator less for signal <$n0020> created at line 150.
    Found 7-bit comparator less for signal <$n0022> created at line 179.
    Found 6-bit subtractor for signal <$n0027> created at line 130.
    Found 3-bit adder for signal <$n0028> created at line 130.
    Found 6-bit subtractor for signal <$n0029> created at line 130.
    Found 3-bit adder for signal <$n0030> created at line 130.
    Found 7-bit comparator less for signal <$n0036> created at line 130.
    Found 7-bit comparator greater for signal <$n0037> created at line 130.
    Found 7-bit comparator less for signal <$n0038> created at line 130.
    Found 7-bit comparator greater for signal <$n0039> created at line 130.
    Found 7-bit adder for signal <$n0040> created at line 182.
    Found 4-bit adder for signal <$n0043> created at line 151.
    Found 25-bit up counter for signal <clkdiv>.
    Found 7-bit register for signal <counter>.
    Found 4-bit register for signal <div_counter>.
    Found 1-bit register for signal <flag>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   6 Adder/Subtracter(s).
	inferred   6 Comparator(s).
	inferred   8 Tristate(s).
Unit <lcd> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
	Encoding for FSM_0 is Sequential flip-flop = T
Dynamic shift register inference ...
!!! UNKNOWN MACRO TYPE : 51 !!!
!!! UNKNOWN MACRO TYPE : 51 !!!
!!! UNKNOWN MACRO TYPE : 51 !!!

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 32x8-bit ROM                      : 1
# Adders/Subtractors               : 6
 4-bit adder                       : 1
 7-bit adder                       : 1
 6-bit subtractor                  : 2
 3-bit adder                       : 2
# Counters                         : 1
 25-bit up counter                 : 1
# Registers                        : 3
 1-bit register                    : 1
 4-bit register                    : 1
 7-bit register                    : 1
# Comparators                      : 6
 7-bit comparator greater          : 2
 7-bit comparator less             : 3
 4-bit comparator less             : 1
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
ERROR:Xst:79 - Model 'fd' has different characteristics in destination library
ERROR:Xst:1831 - Missing ports are:C 
ERROR:Xst:1832 - Unknown ports are:clk 
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Total memory usage is 49172 kilobytes