📄 lcd.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "26 " "Warning: Found 26 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[13\] " "Info: Detected ripple clock \"clkcnt\[13\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[13\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~184 " "Info: Detected gated clock \"Equal0~184\" as buffer" { } { { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~184" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[14\] " "Info: Detected ripple clock \"clkcnt\[14\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[14\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[15\] " "Info: Detected ripple clock \"clkcnt\[15\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[15\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[12\] " "Info: Detected ripple clock \"clkcnt\[12\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[12\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[8\] " "Info: Detected ripple clock \"clkcnt\[8\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[8\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~183 " "Info: Detected gated clock \"Equal0~183\" as buffer" { } { { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~183" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[9\] " "Info: Detected ripple clock \"clkcnt\[9\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[9\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[11\] " "Info: Detected ripple clock \"clkcnt\[11\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[11\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[10\] " "Info: Detected ripple clock \"clkcnt\[10\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[10\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[4\] " "Info: Detected ripple clock \"clkcnt\[4\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[4\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~182 " "Info: Detected gated clock \"Equal0~182\" as buffer" { } { { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~182" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[7\] " "Info: Detected ripple clock \"clkcnt\[7\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[7\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[5\] " "Info: Detected ripple clock \"clkcnt\[5\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[5\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[6\] " "Info: Detected ripple clock \"clkcnt\[6\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[6\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[1\] " "Info: Detected ripple clock \"clkcnt\[1\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~181 " "Info: Detected gated clock \"Equal0~181\" as buffer" { } { { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~181" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[3\] " "Info: Detected ripple clock \"clkcnt\[3\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[2\] " "Info: Detected ripple clock \"clkcnt\[2\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[16\] " "Info: Detected ripple clock \"clkcnt\[16\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[16\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[17\] " "Info: Detected ripple clock \"clkcnt\[17\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[17\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[18\] " "Info: Detected ripple clock \"clkcnt\[18\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[18\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[0\] " "Info: Detected ripple clock \"clkcnt\[0\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkcnt\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~186 " "Info: Detected gated clock \"Equal0~186\" as buffer" { } { { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~186" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkdiv " "Info: Detected ripple clock \"clkdiv\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkdiv" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_int " "Info: Detected ripple clock \"clk_int\" as buffer" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 110 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_int" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register state\[7\] register counter\[3\] 77.88 MHz 12.84 ns Internal " "Info: Clock \"clk\" has Internal fmax of 77.88 MHz between source register \"state\[7\]\" and destination register \"counter\[3\]\" (period= 12.84 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.887 ns + Longest register register " "Info: + Longest register to register delay is 7.887 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[7\] 1 REG LC_X5_Y1_N0 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N0; Fanout = 9; REG Node = 'state\[7\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { state[7] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.740 ns) 1.680 ns Equal3~68 2 COMB LC_X5_Y1_N6 2 " "Info: 2: + IC(0.940 ns) + CELL(0.740 ns) = 1.680 ns; Loc. = LC_X5_Y1_N6; Fanout = 2; COMB Node = 'Equal3~68'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { state[7] Equal3~68 } "NODE_NAME" } } { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.791 ns) + CELL(0.511 ns) 2.982 ns Equal16~39 3 COMB LC_X5_Y1_N2 8 " "Info: 3: + IC(0.791 ns) + CELL(0.511 ns) = 2.982 ns; Loc. = LC_X5_Y1_N2; Fanout = 8; COMB Node = 'Equal16~39'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.302 ns" { Equal3~68 Equal16~39 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 160 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.057 ns) + CELL(0.511 ns) 5.550 ns counter\[4\]~489 4 COMB LC_X5_Y2_N7 7 " "Info: 4: + IC(2.057 ns) + CELL(0.511 ns) = 5.550 ns; Loc. = LC_X5_Y2_N7; Fanout = 7; COMB Node = 'counter\[4\]~489'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.568 ns" { Equal16~39 counter[4]~489 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.094 ns) + CELL(1.243 ns) 7.887 ns counter\[3\] 5 REG LC_X6_Y2_N4 14 " "Info: 5: + IC(1.094 ns) + CELL(1.243 ns) = 7.887 ns; Loc. = LC_X6_Y2_N4; Fanout = 14; REG Node = 'counter\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.337 ns" { counter[4]~489 counter[3] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.005 ns ( 38.10 % ) " "Info: Total cell delay = 3.005 ns ( 38.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.882 ns ( 61.90 % ) " "Info: Total interconnect delay = 4.882 ns ( 61.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.887 ns" { state[7] Equal3~68 Equal16~39 counter[4]~489 counter[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.887 ns" { state[7] Equal3~68 Equal16~39 counter[4]~489 counter[3] } { 0.000ns 0.940ns 0.791ns 2.057ns 1.094ns } { 0.000ns 0.740ns 0.511ns 0.511ns 1.243ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.244 ns - Smallest " "Info: - Smallest clock skew is -4.244 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 15.399 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 15.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 19 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 19; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkcnt\[16\] 2 REG LC_X3_Y3_N0 4 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N0; Fanout = 4; REG Node = 'clkcnt\[16\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clkcnt[16] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.954 ns) + CELL(0.511 ns) 5.189 ns Equal0~186 3 COMB LC_X3_Y3_N4 10 " "Info: 3: + IC(0.954 ns) + CELL(0.511 ns) = 5.189 ns; Loc. = LC_X3_Y3_N4; Fanout = 10; COMB Node = 'Equal0~186'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.465 ns" { clkcnt[16] Equal0~186 } "NODE_NAME" } } { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.740 ns) + CELL(1.294 ns) 7.223 ns clkdiv 4 REG LC_X3_Y3_N9 3 " "Info: 4: + IC(0.740 ns) + CELL(1.294 ns) = 7.223 ns; Loc. = LC_X3_Y3_N9; Fanout = 3; REG Node = 'clkdiv'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.034 ns" { Equal0~186 clkdiv } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.216 ns) + CELL(1.294 ns) 11.733 ns clk_int 5 REG LC_X2_Y3_N2 21 " "Info: 5: + IC(3.216 ns) + CELL(1.294 ns) = 11.733 ns; Loc. = LC_X2_Y3_N2; Fanout = 21; REG Node = 'clk_int'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.510 ns" { clkdiv clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 110 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(0.918 ns) 15.399 ns counter\[3\] 6 REG LC_X6_Y2_N4 14 " "Info: 6: + IC(2.748 ns) + CELL(0.918 ns) = 15.399 ns; Loc. = LC_X6_Y2_N4; Fanout = 14; REG Node = 'counter\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.666 ns" { clk_int counter[3] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.474 ns ( 42.04 % ) " "Info: Total cell delay = 6.474 ns ( 42.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.925 ns ( 57.96 % ) " "Info: Total interconnect delay = 8.925 ns ( 57.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.399 ns" { clk clkcnt[16] Equal0~186 clkdiv clk_int counter[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "15.399 ns" { clk clk~combout clkcnt[16] Equal0~186 clkdiv clk_int counter[3] } { 0.000ns 0.000ns 1.267ns 0.954ns 0.740ns 3.216ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.511ns 1.294ns 1.294ns 0.918ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 19.643 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 19.643 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 19 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 19; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkcnt\[7\] 2 REG LC_X2_Y2_N6 4 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y2_N6; Fanout = 4; REG Node = 'clkcnt\[7\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clkcnt[7] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.875 ns) + CELL(0.914 ns) 5.513 ns Equal0~182 3 COMB LC_X2_Y2_N7 1 " "Info: 3: + IC(0.875 ns) + CELL(0.914 ns) = 5.513 ns; Loc. = LC_X2_Y2_N7; Fanout = 1; COMB Node = 'Equal0~182'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.789 ns" { clkcnt[7] Equal0~182 } "NODE_NAME" } } { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.841 ns) + CELL(0.740 ns) 8.094 ns Equal0~185 4 COMB LC_X2_Y3_N7 1 " "Info: 4: + IC(1.841 ns) + CELL(0.740 ns) = 8.094 ns; Loc. = LC_X2_Y3_N7; Fanout = 1; COMB Node = 'Equal0~185'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.581 ns" { Equal0~182 Equal0~185 } "NODE_NAME" } } { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.139 ns) + CELL(0.200 ns) 9.433 ns Equal0~186 5 COMB LC_X3_Y3_N4 10 " "Info: 5: + IC(1.139 ns) + CELL(0.200 ns) = 9.433 ns; Loc. = LC_X3_Y3_N4; Fanout = 10; COMB Node = 'Equal0~186'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.339 ns" { Equal0~185 Equal0~186 } "NODE_NAME" } } { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.740 ns) + CELL(1.294 ns) 11.467 ns clkdiv 6 REG LC_X3_Y3_N9 3 " "Info: 6: + IC(0.740 ns) + CELL(1.294 ns) = 11.467 ns; Loc. = LC_X3_Y3_N9; Fanout = 3; REG Node = 'clkdiv'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.034 ns" { Equal0~186 clkdiv } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.216 ns) + CELL(1.294 ns) 15.977 ns clk_int 7 REG LC_X2_Y3_N2 21 " "Info: 7: + IC(3.216 ns) + CELL(1.294 ns) = 15.977 ns; Loc. = LC_X2_Y3_N2; Fanout = 21; REG Node = 'clk_int'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.510 ns" { clkdiv clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 110 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(0.918 ns) 19.643 ns state\[7\] 8 REG LC_X5_Y1_N0 9 " "Info: 8: + IC(2.748 ns) + CELL(0.918 ns) = 19.643 ns; Loc. = LC_X5_Y1_N0; Fanout = 9; REG Node = 'state\[7\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.666 ns" { clk_int state[7] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.817 ns ( 39.80 % ) " "Info: Total cell delay = 7.817 ns ( 39.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.826 ns ( 60.20 % ) " "Info: Total interconnect delay = 11.826 ns ( 60.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.643 ns" { clk clkcnt[7] Equal0~182 Equal0~185 Equal0~186 clkdiv clk_int state[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.643 ns" { clk clk~combout clkcnt[7] Equal0~182 Equal0~185 Equal0~186 clkdiv clk_int state[7] } { 0.000ns 0.000ns 1.267ns 0.875ns 1.841ns 1.139ns 0.740ns 3.216ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.740ns 0.200ns 1.294ns 1.294ns 0.918ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.399 ns" { clk clkcnt[16] Equal0~186 clkdiv clk_int counter[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "15.399 ns" { clk clk~combout clkcnt[16] Equal0~186 clkdiv clk_int counter[3] } { 0.000ns 0.000ns 1.267ns 0.954ns 0.740ns 3.216ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.511ns 1.294ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.643 ns" { clk clkcnt[7] Equal0~182 Equal0~185 Equal0~186 clkdiv clk_int state[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.643 ns" { clk clk~combout clkcnt[7] Equal0~182 Equal0~185 Equal0~186 clkdiv clk_int state[7] } { 0.000ns 0.000ns 1.267ns 0.875ns 1.841ns 1.139ns 0.740ns 3.216ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.740ns 0.200ns 1.294ns 1.294ns 0.918ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "lcd.vhd" "" { Text "F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.887 ns" { state[7] Equal3~68 Equal16~39 counter[4]~489 counter[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.887 ns" { state[7] Equal3~68 Equal16~39 counter[4]~489 counter[3] } { 0.000ns 0.940ns 0.791ns 2.057ns 1.094ns } { 0.000ns 0.740ns 0.511ns 0.511ns 1.243ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.399 ns" { clk clkcnt[16] Equal0~186 clkdiv clk_int counter[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "15.399 ns" { clk clk~combout clkcnt[16] Equal0~186 clkdiv clk_int counter[3] } { 0.000ns 0.000ns 1.267ns 0.954ns 0.740ns 3.216ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.511ns 1.294ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.643 ns" { clk clkcnt[7] Equal0~182 Equal0~185 Equal0~186 clkdiv clk_int state[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.643 ns" { clk clk~combout clkcnt[7] Equal0~182 Equal0~185 Equal0~186 clkdiv clk_int state[7] } { 0.000ns 0.000ns 1.267ns 0.875ns 1.841ns 1.139ns 0.740ns 3.216ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.740ns 0.200ns 1.294ns 1.294ns 0.918ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 76 " "Warning: Circuit may not operate. Detected 76 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
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