manifest.skip

Verilog Parser in Perl

^CVS/
/CVS/
^.git/
,v$
\.(bak|old)/
\.(bak|old)$
\bMakefile$
^INSTALL$
\.wpsin$
\.texi$
\.tar\.
\.bs$
\.vpassert/.*
\.o$
\.def$
\.dll$
\.exp$
\.tmp$
\.pre\..*$
_pretmp\..*$
VPreprocLex\.cpp$
simv
.*\.tar\.gz
\bblib\b
pm_to_blib$
Parser/Parser.c
Parser/VParseBison.*\.cpp
Parser/VParseBison.*\.h
Parser/VParseBison.*\.tab.c
Parser/VParseBison.*\.output
Parser/VParseLex.cpp
Parser/VParseLex_pretmp.cpp
Preproc/Preproc.c
Preproc/VPreprocLex_pretmp.cpp
signals.vrename
test_dir
\.svn/