35_sigparser.out

Verilog Parser in Perl

verilog/parser_bugs.v:172: PARAMPIN  '' '0' '3'
verilog/parser_bugs.v:172: PIN  '' 'PT' '1'
verilog/parser_bugs.v:172: PIN  '' 'PU' '2'
verilog/parser_bugs.v:172: PIN  '' '1'b1' '3'
verilog/parser_bugs.v:172: ENDCELL  ''
verilog/parser_bugs.v:173: INSTANT  'pulldown' 'pullinst' ''
verilog/parser_bugs.v:173: PIN  '' 'r' '1'
verilog/parser_bugs.v:173: ENDCELL  ''
verilog/parser_bugs.v:177: INSTANT  'cdrv' 'clk' ''
verilog/parser_bugs.v:177: PIN  '' 'clk' '1'
verilog/parser_bugs.v:177: ENDCELL  ''
verilog/parser_bugs.v:185: SIGNAL_DECL  'wire' '\33escapeneeded ' '' '' '' '1'b1'
verilog/parser_bugs.v:186: SIGNAL_DECL  'wire' '\33escapenewlineend ' '' '' '' '1'b1'
verilog/parser_bugs.v:188: SIGNAL_DECL  'wire' 'noescapenewlineend' '' '' '' '1'b1'
verilog/parser_bugs.v:190: SIGNAL_DECL  'wire' 'noescapespaceend' '' '' '' '1'b1'
verilog/parser_bugs.v:192: ENDMODULE  'endmodule'
verilog/parser_bugs.v:194: MODULE  'module' 'v2kparam' undef '0'
verilog/parser_bugs.v:195: SIGNAL_DECL  'parameter' 'WIDTH' '' '' '' '1'
verilog/parser_bugs.v:196: SIGNAL_DECL  'parameter' 'LENGTH' '' '' '' '1'
verilog/parser_bugs.v:196: SIGNAL_DECL  'parameter' 'LENGTH2' '' '' '' '1'
verilog/parser_bugs.v:197: SIGNAL_DECL  'output' 'myout' '[WIDTH-1:0]' '' '' ''
verilog/parser_bugs.v:197: PORT  'myout'
verilog/parser_bugs.v:198: SIGNAL_DECL  'input' 'myin' '[LENGTH-1:0]' '' '' ''
verilog/parser_bugs.v:198: PORT  'myin'
verilog/parser_bugs.v:198: SIGNAL_DECL  'input' 'myinb' '[LENGTH-1:0]' '' '' ''
verilog/parser_bugs.v:198: PORT  'myinb'
verilog/parser_bugs.v:201: ENDMODULE  'endmodule'
verilog/parser_bugs.v:203: MODULE  'module' 'foreqn' undef '0'
verilog/parser_bugs.v:203: PORT  'in'
verilog/parser_bugs.v:204: SIGNAL_DECL  'input' 'in' '[1:0]' '' '' ''
verilog/parser_bugs.v:205: SIGNAL_DECL  'reg' 'a' '' '' '' ''
verilog/parser_bugs.v:205: SIGNAL_DECL  'reg' 'b' '' '' '' ''
verilog/parser_bugs.v:206: SIGNAL_DECL  'reg' 'c' '[1:0]' '' '' ''
verilog/parser_bugs.v:211: ENDMODULE  'endmodule'
verilog/parser_bugs.v:213: MODULE  'module' 'colonslash' undef '0'
verilog/parser_bugs.v:222: ENDMODULE  'endmodule'
verilog/parser_bugs.v:224: MODULE  'module' 'enums' undef '0'
verilog/parser_bugs.v:225: SIGNAL_DECL  'enum' 'light' '' '' '' ''
verilog/parser_bugs.v:226: SIGNAL_DECL  'integer' 'state' '' '' '' ''
verilog/parser_bugs.v:226: SIGNAL_DECL  'integer' 'next' '' '' '' ''
verilog/parser_bugs.v:227: SIGNAL_DECL  'enum' 'medal' '' '' '' ''
verilog/parser_bugs.v:228: SIGNAL_DECL  'enum' 'E1' '' '' '' ''
verilog/parser_bugs.v:230: SIGNAL_DECL  'logic' 'STATE' '[1:0]' '' '' ''
verilog/parser_bugs.v:230: SIGNAL_DECL  'logic' 'NSTATE' '[1:0]' '' '' ''
verilog/parser_bugs.v:231: ENDMODULE  'endmodule'
verilog/parser_bugs.v:233: MODULE  'module' 'invec' undef '0'
verilog/parser_bugs.v:234: SIGNAL_DECL  'output' 'novec' '' '' '' ''
verilog/parser_bugs.v:234: SIGNAL_DECL  'logic' 'novec' '' '' '' ''
verilog/parser_bugs.v:234: PORT  'novec'
verilog/parser_bugs.v:235: SIGNAL_DECL  'output' 'range' '[7:0]' '' '' ''
verilog/parser_bugs.v:235: SIGNAL_DECL  'logic' 'range' '[7:0]' '' '' ''
verilog/parser_bugs.v:235: PORT  'range'
verilog/parser_bugs.v:236: SIGNAL_DECL  'output' 'arrayAndRange' '[7:0]' '[1:0]' '' ''
verilog/parser_bugs.v:236: SIGNAL_DECL  'logic' 'arrayAndRange' '[7:0]' '[1:0]' '' ''
verilog/parser_bugs.v:236: PORT  'arrayAndRange'
verilog/parser_bugs.v:237: SIGNAL_DECL  'output' 'arrayAndArrayAndRange' '[7:0]' '[2:0][1:0]' '' ''
verilog/parser_bugs.v:237: SIGNAL_DECL  'logic' 'arrayAndArrayAndRange' '[7:0]' '[2:0][1:0]' '' ''
verilog/parser_bugs.v:237: PORT  'arrayAndArrayAndRange'
verilog/parser_bugs.v:238: SIGNAL_DECL  'output' 'novec2' '' '' 'signed' ''
verilog/parser_bugs.v:238: SIGNAL_DECL  'reg' 'novec2' '' '' 'signed' ''
verilog/parser_bugs.v:238: PORT  'novec2'
verilog/parser_bugs.v:240: ENDMODULE  'endmodule'
verilog/parser_bugs.v:242: MODULE  'module' 'bug34575' undef '0'
verilog/parser_bugs.v:243: SIGNAL_DECL  'wire' 'a' '' '' '' ''
verilog/parser_bugs.v:243: SIGNAL_DECL  'wire' 'b' '' '' '' ''
verilog/parser_bugs.v:243: SIGNAL_DECL  'wire' 'c' '' '' '' ''
verilog/parser_bugs.v:243: SIGNAL_DECL  'wire' 'd' '' '' '' ''
verilog/parser_bugs.v:248: ENDMODULE  'endmodule'
verilog/parser_bugs.v:250: MODULE  'module' 'bug34649' undef '0'
verilog/parser_bugs.v:250: PORT  'name'
verilog/parser_bugs.v:251: SIGNAL_DECL  'output' 'name' '' '' '' ''
verilog/parser_bugs.v:251: SIGNAL_DECL  'reg' 'name' '' '' '' '0'
verilog/parser_bugs.v:252: ENDMODULE  'endmodule'
verilog/parser_bugs.v:253: MODULE  'module' 'bug34649b' undef '0'
verilog/parser_bugs.v:254: SIGNAL_DECL  'output' 'name' '' '' '' ''
verilog/parser_bugs.v:254: SIGNAL_DECL  'reg' 'name' '' '' '' ''
verilog/parser_bugs.v:254: PORT  'name'
verilog/parser_bugs.v:256: ENDMODULE  'endmodule'
verilog/parser_bugs.v:257: MODULE  'module' 'bugvp10' undef '0'
verilog/parser_bugs.v:278: ENDMODULE  'endmodule'
verilog/parser_bugs.v:280: MODULE  'module' 'bugvp33' undef '0'
verilog/parser_bugs.v:281: SIGNAL_DECL  'integer' 'i' '' '' '' ''
verilog/parser_bugs.v:289: ENDMODULE  'endmodule'
verilog/parser_bugs.v:291: MODULE  'module' 'bugvp16' undef '0'
verilog/parser_bugs.v:294: ENDMODULE  'endmodule'
verilog/parser_bugs.v:296: SIGNAL_DECL  'parameter' 'bugvp39' '' '' '' '0'
verilog/parser_bugs.v:301: MODULE  'module' 'bugvp64' undef '0'
verilog/parser_bugs.v:302: SIGNAL_DECL  'parameter' 'a' '' '' '' '1'
verilog/parser_bugs.v:302: SIGNAL_DECL  'parameter' 'b' '' '' '' '2'
verilog/parser_bugs.v:303: SIGNAL_DECL  'parameter' 'c' '' '' '' '3.0'
verilog/parser_bugs.v:304: SIGNAL_DECL  'parameter' 'd' '' '' '' '4.0'
verilog/parser_bugs.v:305: SIGNAL_DECL  'parameter' 'e' '' '' '' '5.0'
verilog/parser_bugs.v:306: ENDMODULE  'endmodule'
verilog/parser_bugs.v:308: MODULE  'module' 'bugrt43138' undef '0'
verilog/parser_bugs.v:310: ENDMODULE  'endmodule'
verilog/pinorder.v:006: MODULE  'module' 'pinorder4' undef '0'
verilog/pinorder.v:007: SIGNAL_DECL  'wire' 'b_i' '' '' '' ''
verilog/pinorder.v:008: SIGNAL_DECL  'wire' 'd_o' '' '' '' ''
verilog/pinorder.v:009: SIGNAL_DECL  'wire' 'a_i' '[7:0]' '' '' ''
verilog/pinorder.v:010: SIGNAL_DECL  'wire' 'IPCD_const' '[31:0]' '' '' '32'h1'
verilog/pinorder.v:015: INSTANT  'foo' 'foo1' ''
verilog/pinorder.v:015: PIN  'y' 'b_i' '1'
verilog/pinorder.v:015: PIN  'x' 'a_i' '2'
verilog/pinorder.v:015: PIN  'abcconst' '3'h0' '3'
verilog/pinorder.v:015: PIN  'noconnect' '' '4'
verilog/pinorder.v:016: PIN  'def' 'IPCD_const' '5'
verilog/pinorder.v:016: ENDCELL  ''
verilog/pinorder.v:017: INSTANT  'foo' 'foo3' ''
verilog/pinorder.v:017: PIN  '' 'b_i' '1'
verilog/pinorder.v:017: PIN  '' 'a_i' '2'
verilog/pinorder.v:017: PIN  '' '3'h0' '3'
verilog/pinorder.v:017: PIN  '' 'IPCD_const' '5'
verilog/pinorder.v:017: ENDCELL  ''
verilog/pinorder.v:018: INSTANT  'foo2' 'foo2' ''
verilog/pinorder.v:018: PIN  '' 'b_i' '1'
verilog/pinorder.v:018: PIN  '' 'a_i[0]' '2'
verilog/pinorder.v:018: PIN  '' 'd_o' '3'
verilog/pinorder.v:018: ENDCELL  ''
verilog/pinorder.v:020: ENDMODULE  'endmodule'
verilog/pinorder.v:022: MODULE  'module' 'foo2' undef '0'
verilog/pinorder.v:024: PORT  'x'
verilog/pinorder.v:026: PORT  'z'
verilog/pinorder.v:026: PORT  'y'
verilog/pinorder.v:028: SIGNAL_DECL  'input' 'z' '' '' '' ''
verilog/pinorder.v:029: SIGNAL_DECL  'input' 'y' '' '' '' ''
verilog/pinorder.v:030: SIGNAL_DECL  'output' 'x' '' '' '' ''
verilog/pinorder.v:031: SIGNAL_DECL  'reg' 'x' '' '' '' ''
verilog/pinorder.v:033: ENDMODULE  'endmodule'
verilog/pinorder.v:035: MODULE  'module' 'foo' undef '0'
verilog/pinorder.v:037: PORT  'y'
verilog/pinorder.v:037: PORT  'x'
verilog/pinorder.v:037: PORT  'abcconst'
verilog/pinorder.v:037: PORT  'noconnect'
verilog/pinorder.v:037: PORT  'def'
verilog/pinorder.v:039: SIGNAL_DECL  'input' 'y' '' '' '' ''
verilog/pinorder.v:040: SIGNAL_DECL  'input' 'x' '' '' '' ''
verilog/pinorder.v:041: SIGNAL_DECL  'input' 'abcconst' '[2:0]' '' '' ''
verilog/pinorder.v:042: SIGNAL_DECL  'input' 'noconnect' '[3:0]' '' 'signed' ''
verilog/pinorder.v:043: SIGNAL_DECL  'input' 'def' '[31:0]' '' '' ''
verilog/pinorder.v:044: ENDMODULE  'endmodule'
verilog/parser_sv.v:001: PACKAGE  'package' 'mypackage'
verilog/parser_sv.v:002: SIGNAL_DECL  'bit' 'pkg_addr' '[7:0]' '' '' ''
verilog/parser_sv.v:003: SIGNAL_DECL  'bit' 'pkg_data' '[7:0]' '' '' ''
verilog/parser_sv.v:004: ENDPACKAGE  'endpackage'
verilog/parser_sv.v:006: MODULE  'module' 'times' undef '0'
verilog/parser_sv.v:007: SIGNAL_DECL  'time' 'x' '' '' '' ''
verilog/parser_sv.v:009: ENDMODULE  'endmodule'
verilog/parser_sv.v:011: INTERFACE  'interface' 'itf'
verilog/parser_sv.v:011: SIGNAL_DECL  'parameter' 'num_of_cli' '' '' '' '0'
verilog/parser_sv.v:012: SIGNAL_DECL  'logic' 'blabla' '' '' '' ''
verilog/parser_sv.v:013: SIGNAL_DECL  'logic' 'addr' '[7:0]' '' '' ''
verilog/parser_sv.v:013: SIGNAL_DECL  'logic' 'data' '[7:0]' '' '' ''
verilog/parser_sv.v:015: ENDINTERFACE  'endinterface'
verilog/parser_sv.v:017: MODULE  'module' 'test' undef '0'
verilog/parser_sv.v:018: INSTANT  'itf' 'whole_int' ''
verilog/parser_sv.v:018: PORT  'whole_int'
verilog/parser_sv.v:019: INSTANT  'itf' '*' ''
verilog/parser_sv.v:019: PORT  'test'
verilog/parser_sv.v:020: SIGNAL_DECL  'input' 'clk' '' '' '' ''
verilog/parser_sv.v:020: SIGNAL_DECL  'logic' 'clk' '' '' '' ''
verilog/parser_sv.v:020: PORT  'clk'
verilog/parser_sv.v:020: SIGNAL_DECL  'input' 'rst' '' '' '' ''
verilog/parser_sv.v:020: SIGNAL_DECL  'logic' 'rst' '' '' '' ''
verilog/parser_sv.v:020: PORT  'rst'
verilog/parser_sv.v:021: SIGNAL_DECL  'input' 'd_in' '' '' '' ''
verilog/parser_sv.v:021: SIGNAL_DECL  'logic' 'd_in' '' '' '' ''
verilog/parser_sv.v:021: PORT  'd_in'
verilog/parser_sv.v:022: SIGNAL_DECL  'output' 'd_out' '' '' '' ''
verilog/parser_sv.v:022: SIGNAL_DECL  'logic' 'd_out' '' '' '' ''
verilog/parser_sv.v:022: PORT  'd_out'
verilog/parser_sv.v:027: SIGNAL_DECL  'logic' 'd_int' '' '' '' ''
verilog/parser_sv.v:028: SIGNAL_DECL  'logic' 'data_' '[7:0]' '' '' ''
verilog/parser_sv.v:046: ENDMODULE  'endmodule'