📄 42_dumpcheck_2.out
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Module:foo File:verilog/pinorder.v Port:abcconst Dir:in Type:wire Array: Port:def Dir:in Type:wire Array: Port:noconnect Dir:in Type:wire Array: Port:x Dir:in Type:wire Array: Port:y Dir:in Type:wire Array: Net:abcconst O Type:wire Array: 2:0 Net:def O Type:wire Array: 31:0 Net:noconnect O Type:wire Array: 3:0 Net:x O Type:wire Array: Net:y O Type:wire Array:Module:foo2 File:verilog/pinorder.v Port:x Dir:out Type:wire Array: Port:y Dir:in Type:wire Array: Port:z Dir:in Type:wire Array: Net:x I Type:reg Array: Net:y O Type:wire Array: Net:z O Type:wire Array:Module:pinorder4 File:verilog/pinorder.v Net:IPCD_const I Type:wire Array: 31:0 Value:32'h1 Net:a_i I Type:wire Array: 7:0 Net:b_i IO Type:wire Array: Net:d_o I Type:wire Array: Cell:foo1 is-a:foo Module:foo File:verilog/pinorder.v Pin:abcconst Net:3'h0 Port:abcconst Dir:in Type:wire Array: Pin:def Net:IPCD_const Port:def Dir:in Type:wire Array: Net:IPCD_const I Type:wire Array: 31:0 Value:32'h1 Pin:noconnect Net: Port:noconnect Dir:in Type:wire Array: Pin:x Net:a_i Port:x Dir:in Type:wire Array: Net:a_i I Type:wire Array: 7:0 Pin:y Net:b_i Port:y Dir:in Type:wire Array: Net:b_i IO Type:wire Array: Cell:foo2 is-a:foo2 Module:foo2 File:verilog/pinorder.v Pin:x Net:b_i Port:x Dir:out Type:wire Array: Net:b_i IO Type:wire Array: Pin:y Net:d_o Port:y Dir:in Type:wire Array: Net:d_o I Type:wire Array: Pin:z Net:a_i[0] Port:z Dir:in Type:wire Array: Cell:foo3 is-a:foo Module:foo File:verilog/pinorder.v Pin:abcconst Net:3'h0 Port:abcconst Dir:in Type:wire Array: Pin:def Net:IPCD_const Port:def Dir:in Type:wire Array: Net:IPCD_const I Type:wire Array: 31:0 Value:32'h1 Pin:x Net:a_i Port:x Dir:in Type:wire Array: Net:a_i I Type:wire Array: 7:0 Pin:y Net:b_i Port:y Dir:in Type:wire Array: Net:b_i IO Type:wire Array:
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