42_dumpcheck_2e.out

Verilog Parser in Perl

module foo (
   abcconst, def, noconnect, x, y);
   input [2:0] abcconst;
   input [31:0] def;
   input signed [3:0] noconnect;
   input x;
   input y;
endmodule

module pinorder4 (
   );
   wire [7:0] a_i;
   wire b_i;
   wire d_o;
   foo foo1 (.abcconst(3'h0), .noconnect(), .y(b_i));
   foo2 foo2 (.x(b_i), .y(d_o), .z(a_i[0]));
endmodule