42_dumpcheck_v2k.out

来自「Verilog Parser in Perl」· OUT 代码 · 共 11 行

Module:v_v2k  File:verilog/v_v2k.v
  Port:clk  Dir:in  Type:wire  Array:
  Port:rst  Dir:in  Type:wire  Array:
  Port:sig1  Dir:in  Type:wire  Array:
  Port:sig2  Dir:out  Type:wire  Array:
  Net:WIDTH    Type:parameter  Array:  Value:16
  Net:clk  O  Type:wire  Array:
  Net:rst  O  Type:wire  Array:
  Net:sig1  O  Type:wire  Array:  WIDTH:0
  Net:sig2  I  Type:reg  Array:  WIDTH:0