50_vrename.out

来自「Verilog Parser in Perl」· OUT 代码 · 共 19 行

# Generated by vrename on Thu Jul  5 09:01:51 2007
#
# Files read for this analysis:
vfile	"verilog/test.v"
#
#	Original Signal Name		Name to change to
#	--------------------		-----------------
#
sigren	"a"				"a"				#verilog/test.v 
sigren	"b"				"b"				#verilog/test.v 
sigren	"example"			"example"			#verilog/test.v 
sigren	"result"			"result"			#verilog/test.v 
sigren	"z"				"z"				#verilog/test.v 
#
# Use M-x compile in emacs to automatically perform the changes:
## Local Variables: ***
## compile-command: "./vrename -change verilog/test.v " ***
## End: ***