56_editfiles_b.out

Verilog Parser in Perl

// Created by 56_editfiles.t from 56_editfiles.v

b_front_matter;

`celldefine
// lint_checking HEADER
`ifdef B_HAS_X
module b;
`elsif
module b (input x);
`endif
   wire inside_module_b;
`ifndef SYNTHESIS
   wire in_translate_off;
`endif //SYNTHESIS
endmodule
`endcelldefine