vparsebison.y

Verilog Parser in Perl

//************************************************
// Typedef

data_declaration:		// ==IEEE: data_declaration (INCOMPLETE)
//		dataDeclarationType  list_of_variable_decl_assignments ';'	{ }
		type_declaration			{ }
//	|	package_import_declaration		{ }
//	|	virtual_interface_declaration
	;

// Needs a lot of work
type_declaration:		// ==IEEE: type_declaration (INCOMPLETE)
		yTYPEDEF data_type yaID variable_dimensionE ';'	{ }
//	|	yTYPEDEF yaID '.' yaID yaID ';'		{ }
	|	yTYPEDEF yENUM yaID ';'			{ }
	|	yTYPEDEF ySTRUCT yaID ';'		{ }
	|	yTYPEDEF yUNION yaID ';'		{ }
	|	yTYPEDEF yCLASS yaID ';'		{ }
	;

variable_dimensionE:
		/* empty */				{ }
//	|	variable_dimension			{ }
	;

//************************************************
// Module Items

module_itemListE:		// IEEE: Part of module_declaration
		/* empty */				{ }
	|	module_itemList				{ }
	;

module_itemList:		// IEEE: Part of module_declaration
		module_item				{ }
	|	module_itemList module_item		{ }
	;

module_item:			// ==IEEE: module_item
	//			// IEEE: non_port_module_item
		generate_region				{ }
	|	module_or_generate_item			{ }
	|	specify_block				{ }
	;

generate_region:		// ==IEEE: generate_region
		yGENERATE genTopBlock yENDGENERATE	{ }
	;

// IEEE: module_or_generate_item + module_common_item + parameter_override
module_or_generate_item:
	//			// IEEE: always_construct
		yALWAYS stmtBlock			{ }
	|	continuous_assign			{ }
	|	initial_construct			{ }
	|	final_construct				{ }
	//
	|	yDEFPARAM list_of_defparam_assignments ';'	{ }
	|	package_import_declaration		{ }
	|	instDecl 				{ }
	|	task_declaration			{ }
	|	function_declaration			{ }
	|	portDecl	 			{ }
	|	varDecl 				{ }
	|	combinational_body			{ }
	//
	|	concurrent_assertion_item		{ }  // IEEE puts in module_item, all tools put here
	|	clocking_declaration			{ }
	//
	|	error ';'				{ }
	;

continuous_assign:		// IEEE: continuous_assign
		yASSIGN strengthSpecE delayE assignList ';'	{ }
	;

initial_construct:		// IEEE: initial_construct
		yINITIAL stmtBlock			{ }
	;

final_construct:		// IEEE: final_construct
		yFINAL stmtBlock			{ }
	;

//************************************************
// Generates

// Because genItemList includes variable declarations, we don't need beginNamed
generate_block_or_null:		// IEEE: generate_block_or_null
		genItem					{ }
	|	genItemBegin				{ }
	;

genTopBlock:
		genItemList				{ }
	|	genItemBegin				{ }
	;

genItemBegin:			// IEEE: part of generate_block
		yBEGIN genItemList yEND			{ }
	|	yBEGIN yEND				{ }
	|	yaID ':' yBEGIN genItemList yEND endLabelE	{ }
	|	yaID ':' yBEGIN             yEND endLabelE	{ }
	|	yBEGIN ':' yaID genItemList yEND endLabelE	{ }
	|	yBEGIN ':' yaID             yEND endLabelE	{ }
	;

genItemList:
		genItem					{ }
	|	genItemList genItem			{ }
	;

genItem:			// IEEE: module_or_interface_or_generate_item (INCOMPLETE)
		module_or_generate_item			{ }
	|	conditional_generate_construct		{ }
	|	loop_generate_construct			{ }
	;

conditional_generate_construct:	// ==IEEE: conditional_generate_construct
		yCASE  '(' expr ')' case_generate_itemListE yENDCASE	{ }
	|	yIF '(' expr ')' generate_block_or_null	%prec prLOWER_THAN_ELSE	{ }
	|	yIF '(' expr ')' generate_block_or_null yELSE generate_block_or_null	{ }
	;

loop_generate_construct:	// ==IEEE: loop_generate_construct
		yFOR '(' varRefBase '=' expr ';' expr ';' varRefBase '=' expr ')' generate_block_or_null
			{ }
	;

case_generate_itemListE:	// IEEE: [{ case_generate_itemList }]
		/* empty */				{ }
	|	case_generate_itemList			{ }
	;

case_generate_itemList:		// IEEE: { case_generate_itemList }
		case_generate_item			{ }
	|	case_generate_itemList case_generate_item	{ }
	;

case_generate_item:		// ==IEEE: case_generate_item
		caseCondList ':' generate_block_or_null	{ }
	|	yDEFAULT ':' generate_block_or_null	{ }
	|	yDEFAULT generate_block_or_null		{ }
	;

//************************************************
// Assignments and register declarations

variable_lvalue<str>:		// IEEE: variable_lvalue or net_lvalue
		varRefDotBit				{ $<fl>$=$<fl>1; $$ = $1; }
	|	'{' variable_lvalueList '}'		{ $<fl>$=$<fl>1; $$ = $1+$2+$3; }
	;

variable_lvalueList<str>:	// IEEE: part of variable_lvalue: variable_lvalue { ',' variable_lvalue }
		variable_lvalue				{ $<fl>$=$<fl>1; $$ = $1; }
	|	variable_lvalueList ',' variable_lvalue	{ $<fl>$=$<fl>1; $$ = $1+","+$3; }
	;

assignList:
		assignOne				{ }
	|	assignList ',' assignOne		{ }
	;

assignOne:
		variable_lvalue '=' expr		{ }
	;

delayOrEvE:		// IEEE: delay_or_event_control plus empty
		/* empty */				{ }
	|	delay_control				{ } /* ignored */
	|	event_control				{ } /* ignored */
	|	yREPEAT '(' expr ')' delayOrEvE		{ } /* ignored */
	;

delayE:
		/* empty */				{ }
	|	delay_control				{ } /* ignored */
	;

delay_control:		// ==IEEE: delay_control
		'#' dlyTerm				{ } /* ignored */
	|	'#' '(' minTypMax ')'			{ } /* ignored */
	|	'#' '(' minTypMax ',' minTypMax ')'		{ } /* ignored */
	|	'#' '(' minTypMax ',' minTypMax ',' minTypMax ')'	{ } /* ignored */
	;

dlyTerm:
		yaID 					{ }
	|	yaINTNUM 				{ }
	|	yaFLOATNUM 				{ }
	|	yaTIMENUM 				{ }
	;

minTypMax:			// IEEE: mintypmax_expression and constant_mintypmax_expression
		expr 					{ }
	|	expr ':' expr ':' expr			{ }
	;

sigAndAttr<str>:
		sigId sigAttrListE			{ $<fl>$=$<fl>1; $$=$1; }
	;

netSigList:
		netSig  				{ }
	|	netSigList ',' netSig		       	{ }
	;

netSig:
		sigId sigAttrListE			{ }
	|	yaID  sigAttrListE '=' expr		{ VARDONE($<fl>1, $1, $4); }
	|	sigIdRange sigAttrListE			{ }
	;

sigIdRange:
		yaID rangeList				{ $<fl>$=$<fl>1; VARARRAY($2); VARDONE($<fl>1, $1, ""); }
	;

regSigId<str>:
		yaID rangeListE				{ $<fl>$=$<fl>1; VARARRAY($2); VARDONE($<fl>1, $1, ""); }
	|	yaID rangeListE '=' constExpr		{ $<fl>$=$<fl>1; VARARRAY($2); VARDONE($<fl>1, $1, $4); }
	;

sigId<str>:
		yaID					{ $<fl>$=$<fl>1; VARDONE($<fl>1, $1, ""); }
	;

sigList:
		sigInit					{ }
	|	sigList ',' sigInit			{ }
	;

sigInit:
		sigAndAttr				{ }
	|	sigAndAttr '=' expr			{ }
	;

regsig:
		regSigId sigAttrListE			{}
	;

sigAttrListE:
		/* empty */				{}
	;

rangeListE<str>:
		/* empty */    		               	{ $$ = ""; }
	|	rangeList 				{ $$ = $1; }
	;

rangeList<str>:			// IEEE: packed_dimension + ...
		anyrange				{ $$ = $1; }
        |	rangeList anyrange			{ $$ = $1+$2; }
	;

regrangeE<str>:
		/* empty */    		               	{ VARRANGE(""); }
	|	anyrange 				{ VARRANGE($1); }
	;

regArRangeE:
		/* empty */    		               	{ }
	|	regArRangeList 				{ }
	;

// Complication here is "[#:#]" is a range, while "[#:#][#:#]" is an array and range.
regArRangeList:
		anyrange				{ VARRANGE($1); }
        |	regArRangeList anyrange			{ VARARRAY(GRAMMARP->m_varArray+GRAMMARP->m_varRange); VARRANGE($2); }
	;

anyrange<str>:
		'[' constExpr ':' constExpr ']'		{ $$ = "["+$2+":"+$4+"]"; }
	;

delayrange:
		regrangeE delayE 			{ }
	|	ySCALARED regrangeE delayE 		{ }
	|	yVECTORED regrangeE delayE		{ }
	;

portRangeE<str>:
		/* empty */	                   	{ $$ = ""; }
	|	'[' constExpr ']'              		{ $$ = "["+$2+"]"; }
	|	'[' constExpr ':' constExpr  ']'    	{ $$ = "["+$2+":"+$4+"]"; }
	;

//************************************************
// Parameters

param:
		yaID sigAttrListE '=' expr		{ $<fl>$=$<fl>1; VARDONE($<fl>1, $1, $4); }
	;

paramList:
		param					{ }
	|	paramList ',' param			{ }
	;

list_of_defparam_assignments:	// ==IEEE: list_of_defparam_assignments
		defparam_assignment			{ }
	|	list_of_defparam_assignments ',' defparam_assignment	{ }
	;

defparam_assignment:		// ==IEEE: defparam_assignment
		varRefDotBit '=' expr 		{ }
	;

//************************************************
// Instances
// We don't know if its a gate or module or udp instantiation
//   modname        [#(params)]  name  (pins) [, name ...]
//   gate (strong0) [#(delay)]  [name] (pins) [, (pins)...]

instDecl:			// IEEE: module_instantiation + gate_instantiation + udp_instantiation
		instModName {INSTPREP($1,1);} strengthSpecE instparamListE {INSTPREP($1,0);} instnameList ';'
		 	{ }
	;

instModName<str>:
		yaID 					{ $<fl>$=$<fl>1; $$ = $1; }
	|	gateKwd			 		{ $<fl>$=$<fl>1; $$ = $1; }
	;

instparamListE:
		/* empty */				{ }
	|	'#' '(' cellpinList ')'			{ }
	|	'#' dlyTerm				{ }
	;

instnameList:
		instnameParen				{ }
	|	instnameList ',' instnameParen		{ }
	;

instnameParen:
		instname cellpinList ')'		{ PARSEP->endcellCb($<fl>3,""); }
	;

instname:
		yaID instRangeE '(' 			{ PARSEP->instantCb($<fl>1, GRAMMARP->m_cellMod, $1, $2); PINPARAMS(); }
	|	instRangeE '(' 				{ PARSEP->instantCb($<fl>2, GRAMMARP->m_cellMod, "", $1); PINPARAMS(); } // UDP
	;

instRangeE<str>:
		/* empty */				{ $$ = ""; }
	|	'[' constExpr ':' constExpr ']'		{ $$ = "["+$2+":"+$4+"]"; }
	;

cellpinList:
		{ } cellpinItList			{ }
	;

cellpinItList:
		cellpinItemE				{ }
	|	cellpinItList ',' cellpinItemE		{ }
	;

cellpinItemE:
		/* empty: ',,' is legal */		{ GRAMMARP->pinNumInc(); }  /*PINDONE(yylval.fl,"",""); <- No, as then () implys a pin*/
	|	yP_DOTSTAR				{ PINDONE($<fl>1,"*","*");GRAMMARP->pinNumInc(); }
	|	'.' yaID				{ PINDONE($<fl>1,$2,$2);  GRAMMARP->pinNumInc(); }
	|	'.' yaID '(' ')'			{ PINDONE($<fl>1,$2,"");  GRAMMARP->pinNumInc(); }
	|	'.' yaID '(' expr ')'			{ PINDONE($<fl>1,$2,$4);  GRAMMARP->pinNumInc(); }
	|	expr					{ PINDONE($<fl>1,"",$1);  GRAMMARP->pinNumInc(); }
	;

//************************************************
// EventControl lists

event_control:			// ==IEEE: event_control (INCOMPLETE)
		'@' '(' senList ')'			{ }
	|	'@' senitemVar				{ }
	|	'@' '(' '*' ')'				{ }
	|	'@' '*'					{ }  /* Verilog 2001 */
//	|	'@' sequence_instance			{ }
	;

senList:			// IEEE: event_expression - split over several
		senitem					{ }
	|	senList yOR senitem			{ }
	|	senList ',' senitem			{ }	/* Verilog 2001 */
	;

senitem:
		senitemEdge				{ }
	|	expr					{ }
	;

senitemVar:
		varRefDotBit				{ }
	;

senitemEdge:			// IEEE: part of event_expression
		yPOSEDGE expr				{ }
	|	yPOSEDGE expr yIFF expr			{ }
	|	yNEGEDGE expr				{ }
	|	yNEGEDGE expr yIFF expr			{ }
	;

//************************************************
// Statements

stmtBlock:		// IEEE: statement + seq_block + par_block
		stmt					{ }
	|	yBEGIN stmtList yEND			{ }
	|	yBEGIN yEND				{ }
	|	beginNamed stmtList yEND endLabelE	{ }
	|	beginNamed 	    yEND endLabelE	{ }
	|	yFORK stmtList	   yJOIN		{ }
	|	yFORK 		   yJOIN		{ }
	|	forkNamed stmtList yJOIN endLabelE	{ }
	|	forkNamed 	   yJOIN endLabelE	{ }
	;

beginNamed:
		yBEGIN ':' yaID varDeclList		{ }
	|	yBEGIN ':' yaID 			{ }
	;

forkNamed:
		yFORK ':' yaID varDeclList		{ }
	|	yFORK ':' yaID 				{ }
	;

stmtList:
		stmtBlock				{ }
	|	stmtList stmtBlock			{ }
	;

// IEEE: statement_or_null (may include more stuff, not analyzed)
//	== function_statement_or_null
stmt:
	//			// from _or_null
		';'					{ }
	|	labeledStmt				{ }
	|	yaID ':' labeledStmt			{ }  /*S05 block creation rule*/

	//			// IEEE: operator_assignment
	//			// added delayOrEvE as code found that expected it - maybe Verilog-XL accepted it?
	|	variable_lvalue '=' 		delayOrEvE expr ';'	{ }
	|	variable_lvalue yP_PLUSEQ	expr ';'	{ }
	|	variable_lvalue yP_MINUSEQ	expr ';'	{ }
	|	variable_lvalue yP_TIMESEQ	expr ';'	{ }
	|	variable_lvalue yP_DIVEQ	expr ';'	{ }
	|	variable_lvalue yP_MODEQ	expr ';'	{ }
	|	variable_lvalue yP_ANDEQ	expr ';'	{ }
	|	variable_lvalue yP_OREQ	expr ';'	{ }
	|	variable_lvalue yP_XOREQ	expr ';'	{ }
	|	variable_lvalue yP_SLEFTEQ	expr ';'	{ }
	|	variable_lvalue yP_SRIGHTEQ	expr ';'	{ }
	|	variable_lvalue yP_SSRIGHTEQ	expr ';'	{ }

	//			// IEEE: nonblocking_assignment
	|	variable_lvalue yP_LTE	delayOrEvE expr ';'	{ }

	//			// IEEE: procedural_continuous_assignment