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📄 vparsebison.y

📁 Verilog Parser in Perl
💻 Y
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	| 	yTIMEPRECISION  yaTIMENUM ';' yTIMEUNIT       yaTIMENUM ';'	{ }	;//**********************************************************************// Packagespackage_declaration:		// ==IEEE: package_declaration		packageHdr package_itemListE yENDPACKAGE endLabelE			{ PARSEP->endpackageCb($<fl>3,$3); }	;packageHdr:		yPACKAGE yaID ';'			{ PARSEP->packageCb($<fl>1,$1, $2); }	;package_itemListE:		// IEEE: [{ package_item }]		/* empty */				{ }	|	package_itemList			{ }	;package_itemList:		// IEEE: { package_item }		package_item				{ }	|	package_itemList package_item		{ }	;package_item:			// ==IEEE: package_item		package_or_generate_item_declaration	{ }//	|	anonymous_program			{ }//	|	timeunits_declaration			{ }	;package_or_generate_item_declaration:	// ==IEEE: package_or_generate_item_declaration	//			// varDecl == net_declatation | data_declaration		varDecl					{ }//	|	task_declaration			{ }//	|	function_declaration			{ }//	|	dpi_import_export			{ }//	|	extern_constraint_declaration		{ }	|	class_declaration			{ }//	|	class_constructor_declaration		{ }//	|	parameter_declaration ';'		{ }//	|	local_parameter_declaration		{ }//	|	covergroup_declaration			{ }//	|	overload_declaration			{ }//	|	concurrent_assertion_item_declaration	{ }	|	';'					{ }	;package_import_declaration:	// ==IEEE: package_import_declaration		yIMPORT package_import_itemList ';'	{ }	;package_import_itemList:		package_import_item			{ }	|	package_import_itemList ',' package_import_item { }	;package_import_item:		// ==IEEE: package_import_item		yaID yP_COLONCOLON yaID			{ PARSEP->importCb($<fl>1,$1);}	|	yaID yP_COLONCOLON '*'			{ }	;//**********************************************************************// Module headersmodule_declaration:		// ==IEEE: module_declaration (incomplete)		modHeader timeunits_declarationE module_itemListE yENDMODULE endLabelE			{ PARSEP->endmoduleCb($<fl>4,$4); }	;modHeader:			// IEEE: module_nonansi_header + module_ansi_header		modHdr parameter_port_listE modPortsStarE ';'			{ }	;modHdr:		yMODULE lifetimeE yaID			{ PARSEP->moduleCb($<fl>1,$1,$3,PARSEP->inCellDefine()); }	;parameter_port_listE:		// IEEE: parameter_port_list + empty == parameter_value_assignment		/* empty */				{ }	|	'#' '(' ')'				{ }	|	'#' '(' modParArgs ')'			{ }	;modParArgs:		modParDecl				{ }	|	modParDecl ',' modParList		{ }	;modParList:		modParSecond				{ }	|	modParList ',' modParSecond		{ }	;// Called only after a comma in a v2k list, to allow parsing "parameter a,b, parameter x"modParSecond:		modParDecl				{ }	|	param					{ }	;modPortsStarE:		/* empty */					{ }	|	'(' ')'						{ }	//			// .* expanded from module_declaration	|	'(' yP_DOTSTAR ')'				{ }	|	'(' {GRAMMARP->pinNum(1);} portOrIfList ')'	{ }	|	'(' {GRAMMARP->pinNum(1);} portV2kArgs ')'	{ }	;portOrIfList:		portList				{ }	|	portIfList				{ }	|	portIfList ',' portList			{ }	|	portIfList ',' portV2kArgs		{ }	|	portIfList ',' portList ',' portV2kArgs	{ }	;portList:		port					{ }	|	portList ',' port	 		{ }	;port:		yaID portRangeE				{ PARSEP->portCb($<fl>1, $1); }	;portV2kArgs:		portV2kDecl				{ }	|	portV2kDecl ',' portV2kList		{ }	;portV2kList:		portV2kSecond				{ }	|	portV2kList ',' portV2kSecond		{ }	;// Called only after a comma in a v2k list, to allow parsing "input a,b"portV2kSecond:		portV2kDecl				{ }	|	portV2kInit				{ }	;portV2kInit:		portV2kSig				{ }	|	portV2kSig '=' expr			{ }	;portV2kSig:		sigAndAttr				{ $<fl>$=$<fl>1; PARSEP->portCb($<fl>1, $1); }	;portIfList:		portIf					{ }	|	portIfList ',' portIf			{ }	;portIf:		yaID yaID				{ PARSEP->instantCb($<fl>1, $1, $2, ""); PARSEP->portCb($<fl>1, $2); }	|	yINTERFACE yaID				{ PARSEP->portCb($<fl>1, $2); }	|	yaID '.' yaID yaID			{ PARSEP->instantCb($<fl>1, $1, "*", ""); PARSEP->portCb($<fl>1, $3); }	;//**********************************************************************// Interface headersinterface_declaration:		// IEEE: interface_declaration + interface_nonansi_header + interface_ansi_header:	//			// timeunits_delcarationE is instead in interface_item		intHdr parameter_port_listE modPortsStarE ';' timeunits_declarationE interface_itemListE yENDINTERFACE endLabelE			{ PARSEP->endinterfaceCb($<fl>7,$7); }	|	yEXTERN	intHdr parameter_port_listE modPortsStarE ';'	{ }	;intHdr:		yINTERFACE lifetimeE yaID		{ PARSEP->interfaceCb($<fl>1,$1,$3); }	;interface_itemListE:		/* empty */				{ }	|	interface_itemList			{ }	;interface_itemList:		interface_item				{ }	|	interface_itemList interface_item	{ }	;interface_item:			// IEEE: interface_item + non_port_interface_item		varDecl					{ }	//			// IEEE: non_port_interface_item	|	generate_region				{ }	|	interface_or_generate_item		{ }	|	interface_declaration			{ }	//|	program_declaration	;interface_or_generate_item:	// ==IEEE: interface_or_generate_item		modport_declaration			{ }	//|	moduleCommonItem			{ }	//|	extern_tf_declaration			{ }	;modport_declaration:		// ==IEEE: modport_declaration		yMODPORT modportItemList ';'		{ }	;modportItemList:		modport_item				{ }	|	modportItemList ',' modport_item	{ }	;modport_item:			// ==IEEE: modport_item		yaID '(' modportPortsDeclList ')'	{ }modportPortsDeclList:		modportPortsDecl			{ }	|	modportPortsDeclList ',' modportPortsDecl	{ }	;// IEEE: modport_ports_declaration  + modport_simple_ports_declaration//	+ (modport_tf_ports_declaration+import_export) + modport_clocking_declaration// We've expanded the lists each take to instead just have standalone ID ports.// We track the type as with the V2k series of defines, then create as each ID is seen.modportPortsDecl:		port_direction modportSimplePort	{ }	|	yCLOCKING yaID				{ }	|	yIMPORT modport_tf_port			{ }	|	yEXPORT modport_tf_port			{ }	// Continuations of above after a comma.	|	modportSimplePort			{ }	;//IEEE: modport_simple_port or modport_tf_port, depending what keyword was earliermodportSimplePort:		yaID					{ }	|	'.' yaID '(' ')'			{ }	|	'.' yaID '(' expr ')'			{ }modport_tf_port:		// ==IEEE: modport_tf_port		yaID					{ }//	|	method_prototype	;//************************************************// Variable DeclarationsvarDeclList:		varDecl					{ }	|	varDecl varDeclList			{ }	;regsigList:		regsig 					{ }	|	regsigList ',' regsig			{ }	;portV2kDecl:		varRESET port_direction v2kVarDeclE signingE regArRangeE portV2kInit	{ }//	|	varRESET yaID          portV2kSig	{ }//	|	varRESET yaID '.' yaID portV2kSig	{ }	;portDecl:			// IEEE: port_declaration - plus ';'		varRESET port_direction v2kVarDeclE signingE regArRangeE regsigList ';'	{ }	;varDecl:			// IEEE: net_declaration+reg_declaration due to implicit ambiguity		net_declaration				{ }	|	varRESET data_declaration		{ }	;net_declaration:		// IEEE: net_declaration - excluding implict		varRESET varReg     signingE regArRangeE  regsigList ';'	{ }	//			// IEEE: parameter_declaration plus ';' (INCOMPLETE)	|	varRESET varGParam  signingE regrangeE  paramList ';'		{ }	|	varRESET varGParam  parameter_type      paramList ';'		{ }	//			// IEEE: local_parameter_declaration (INCOMPLETE)	|	varRESET varLParam  signingE regrangeE  paramList ';'		{ }	|	varRESET varLParam  parameter_type      paramList ';'		{ }	//	|	varRESET net_type   strengthSpecE signingE delayrange netSigList ';'	{ }	|	varRESET enumDecl   sigList ';'		{ }	//			// IEEE: genvar_declaration	|	varRESET varGenVar                      regsigList ';'	{ }	;modParDecl:		varRESET varGParam  signingE regrangeE   param 	{ }	;varRESET:		/* empty */ 				{ VARRESET(); }	;net_type:			// ==IEEE: net_type		ySUPPLY0				{ VARDECL($1); }	|	ySUPPLY1				{ VARDECL($1); }	|	yWIRE 					{ VARDECL($1); }	|	yTRI 					{ VARDECL($1); }	|	ygenNETTYPE				{ VARDECL($1); }	;varGParam:	yPARAMETER				{ VARDECL($1); }	;varLParam:	yLOCALPARAM				{ VARDECL($1); }	;varGenVar:	yGENVAR					{ VARDECL($1); }	;varReg:		varTypeKwds				{ VARDECL($1); }	;port_direction:			// ==IEEE: port_direction		yINPUT					{ VARIO($1); }	|	yOUTPUT					{ VARIO($1); }	|	yINOUT					{ VARIO($1); }	|	yREF					{ VARIO($1); }	;parameter_type<str>:		yINTEGER				{ $$=$1; }	|	yREAL					{ $$=$1; }	|	yREALTIME				{ $$=$1; }	|	yTIME					{ $$=$1; }	;varTypeKwds<str>:		integer_type				{ $$=$1; }	|	non_integer_type			{ $$=$1; }	|	ySTRING					{ $<fl>$=$<fl>1; $$=$1; }	|	yEVENT					{ $<fl>$=$<fl>1; $$=$1; }	|	yCHANDLE				{ $<fl>$=$<fl>1; $$=$1; }	;// There's no point in subdividing the integer types into atom/vector// because once we go through a typedef we can't tell them apart.// Later parsing needs to determine if a range is appropriate or not.integer_type<str>:		// ==IEEE: integer_type	//			// IEEE: integer_atom_type		yBYTE					{ $<fl>$=$<fl>1; $$=$1; }	|	ySHORTINT				{ $<fl>$=$<fl>1; $$=$1; }	|	yINT					{ $<fl>$=$<fl>1; $$=$1; }	|	yLONGINT				{ $<fl>$=$<fl>1; $$=$1; }	|	yINTEGER				{ $<fl>$=$<fl>1; $$=$1; }	|	yTIME					{ $<fl>$=$<fl>1; $$=$1; }	//			// IEEE: integer_vector_type	|	yBIT					{ $<fl>$=$<fl>1; $$=$1; }	|	yLOGIC					{ $<fl>$=$<fl>1; $$=$1; }	|	yREG					{ $<fl>$=$<fl>1; $$=$1; }	;non_integer_type<str>:		// ==IEEE: non_integer_type		ySHORTREAL				{ $<fl>$=$<fl>1; $$=$1; }	|	yREAL					{ $<fl>$=$<fl>1; $$=$1; }	|	yREALTIME				{ $<fl>$=$<fl>1; $$=$1; }	;signingE:			// IEEE: signing - plus empty		/*empty*/ 				{ }	|	ySIGNED					{ VARSIGNED("signed"); }	|	yUNSIGNED				{ VARSIGNED("unsigned"); }	;v2kVarDeclE:		/*empty*/ 				{ }	|	net_type				{ }	|	varReg 					{ }	;//************************************************// Enumsdata_type<str>:			// ==IEEE: data_type (INCOMPLETE)		enumDecl				{ $$=$1; }//	|	integer_type signingE regrangeE		{ $$=$1; }//	|	non_integer_type			{ $$=$1; }	|	ySTRUCT        packedSigningE '{' struct_union_memberList '}'	{ }	|	yUNION taggedE packedSigningE '{' struct_union_memberList '}'	{ }//	|	{ packed_dimension }			{ $$=$1; }	|	ySTRING					{ $$=$1; }	|	yCHANDLE				{ $$=$1; }	|	yEVENT					{ $$=$1; }	|	yVIRTUAL yINTERFACE yaID		{ $$=$3; }	|	yVIRTUAL            yaID		{ $$=$2; }//		note need to combine class_scope & package_scope as can't tell which - both "yaID ::"//	|	[ class_scope | package_scope ] type_identifier { packed_dimension }		 { }//	|	class_type				{ $$=$1; }//	|	ps_covergroup_identifier		{ $$=$1; }//	|	type_reference				{ $$=$1; }	;//IEEE: struct_union - not needed, expanded in data_typedata_type_or_void<str>:		// ==IEEE: data_type_or_void		data_type				{ $$=$1; }	|	yVOID					{ $$=$1; }	;struct_union_memberList:	// IEEE: { struct_union_member }		struct_union_member				{ }	|	struct_union_memberList struct_union_member	{ }	;struct_union_member:		// ==IEEE: struct_union_member		random_qualifierE data_type_or_void list_of_variable_decl_assignments ';'	;list_of_variable_decl_assignments:	// ==IEEE: list_of_variable_decl_assignments		/*empty*/				{ }//		FIX lots	;random_qualifierE:		// IEEE: random_qualifier + empty		/*empty*/				{ }	|	yRAND					{ }	|	yRANDC					{ }	;taggedE:		/*empty*/				{ }	|	yTAGGED					{ }	;packedSigningE:		/*empty*/				{ }	|	yPACKED signingE			{ }	;// IEEE: part of data_typeenumDecl<str>:		yENUM enumBaseTypeE '{' enumNameList '}' { $$=$2; }	;enumBaseTypeE<str>:	// IEEE: enum_base_type		/* empty */				{ VARDECL($$="enum"); }	|	integer_type signingE regrangeE		{ VARDECL($$=$1); }	|	yaID regrangeE				{ VARDECL($$=$1); }	;enumNameList:		enum_name_declaration			{ }	|	enumNameList ',' enum_name_declaration	{ }	;enum_name_declaration:		// ==IEEE: enum_name_declaration		yaID enumNameRangeE enumNameStartE	{ }	;enumNameRangeE:			// IEEE: second part of enum_name_declaration		/* empty */				{ }	|	'[' yaINTNUM ']'			{ }	|	'[' yaINTNUM ':' yaINTNUM ']'		{ }	;enumNameStartE:			// IEEE: third part of enum_name_declaration		/* empty */				{ }	|	'=' constExpr				{ }	;

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