changes

Verilog Parser in Perl

Revision history for Perl extension Verilog::Language.

The contributors that suggested a given feature are shown in [].  [by ...]
indicates the contributor was also the author of the fix; Thanks!

* Verilog::Language 3.120 2009/2/25

***	Add vhier --resolve-files option. [by Vasu Arasanipalai]

***     Support "parameter integer" etc, bug64. [Jeff Kurtze]

***	Support big-endian bit vectors, i.e. [0:2], bug65. [Devendra Singh]

***	Return width() of 1 for non-vectored signals, bug65. [Devendra Singh]

***	Add "'{" as an operator.

****	Fix "assign {{x,y},z}", bugrt43138. [Devendra Singh]

****	Fix documentation on ports_ordered, bug66.  [Nicky Ayoub]

****	Fix compile issues with GCC 4.3.  [Donavan Miller]

****	Fix Bison 2.4 compile issues.

* Verilog::Language 3.110 2009/1/28

**	Support interface and import. [by Sandeep Gor]
	Add new SigParser::interface, endinterface and import callbacks.

***	Add vhier --top-module option, bug49.  [John Busco]

***	Add vpassert $ucover_bits_clk. [Mahesh Kumashikar, et al]

***	Add comments to Netlist::Net::verilog_text. [by Jeff Short]

***	Support `pragma and `default_nettype.

* Verilog::Language 3.100 2009/1/2

**	Vppp is now renamed vppreproc; vpm is renamed vpassert.
	This fixes naming conflicts with other packages.  [Chitlesh Goorah]
	Note this breaks backward compatibility and any scripts that call
	these programs will need updating.  Alternatively, add a symlink in
	your bin directory from the old name.

***	Fix missing module dependencies and Bison warning.  [Chitlesh Goorah]

* Verilog::Language 3.045 2008/12/19

***     Add vpm --noline option. [Vasu Arasanipalai]

***     Add vpm --realintent option. [Vasu Arasanipalai]

***	Fix vpm making long lines that upset Cadence's NC-Verilog. [Soon Koh]

****	Fix Makefile issues with ActivePerl.  [Jose Ochoa]

* Verilog::Language 3.044 2008/11/10

***	Support SystemVerilog unique and priority case, bug33. [by Nicky Ayoub]

***	Support SystemVerilog timeunit and timeprecision, bug34. [by Nicky Ayoub]

***	Support SystemVerilog package items, bug39. [by Nick Ayoub]

****	Expand environment variables in Verilog::Getopt.  [Lawrence Butcher]

****	Fix Verilog::EditModules when modules wrapped in ifdef.  [Mat Zeno]

* Verilog::Language 3.043 2008/09/28

***	Ignore Verilog-XL defines (suppress_faults, etc).  [Nicky Ayoub]

****	Fix cpan-testers mis-reporting FAIL when no flex installed.

****	Fix Perl Critic error when not installed, rt39654. [Andreas Koening]

* Verilog::Language 3.042 2008/09/19

***	Add Netlist net, port and module ->delete methods. [Daniel Schoch]

***	Add Netlist modules_sorted_level and ->level method. [Daniel Schoch]

***	Add vpm $uerror_clk and $uwarn_clk assertions.

***	Add vpm $ucover_clk coverage expansions.

***	Vpm now enables `line comments unless using Verilog 1995.

****	Fix verilog_text to output wire values. [by Jeff Short]

****	Fix parsing signals with negative lsbs.  [Stephane Laurent]

* Verilog::Language 3.041 2008/09/03

**	Verilog-Perl development versions are now available from a git server.
	See Installing under http://www.veripool.org/verilog-perl for details.

***     Netlist errors are now always reported through the new
	Verilog::Netlist::Logger class.  This allows errors to be caught or
	specially handled.  [Miguel Corazao, AMD]

****	Fixed code to be Perl::Critic clean.

* Verilog::Language 3.040 2008/08/20

***	Add Netlist::Net->value containing parameter values.  [Ron D Smith]

***	Added Verilog::Netlist/Verilog::Parser preproc option.
	[by Miguel Corazao, AMD]

***	Support +=, -=, etc, and ++, -- operators. [Sean de la Haye]

***	Support "cover property."

****	Eliminated automatic error printing upon application termination.
	[by Miguel Corazao, AMD]

****	Fix syntax error when "`include `defname" is ifdefed.  [John Dickol]

****	Fix error when macro call has commas in concatenate. [John Dickol]

****	Fix compile errors under Fedora 9, GCC 4.3.0.  [by Jeremy Bennett]

* Verilog::Language 3.035 2008/05/07

****	Fix "output reg name=expr;" bug34649 syntax error.  [Martin Scharrer]

****	Fix functions with "input integer".  [Johan Wouters]

****	Fix bug introduced in 3.024 with parametrized defines.

****	Fix compiler warnings under GCC 4.2.1.

****	Fix "endclass" keyword misspelling.  [John Dickol]

****	Fix preprocessor `else after series of `elsif.  [Mark Nodine]

****	Fix parametrized defines calling define with comma.  [Joshua Wise]

* Verilog::Language 3.024 2008/04/02

***	Verilog::Parser will now start parsing using the keywords
	based on the Verilog::Language::language_standard setting.

****	Fix vhier ignoring --language option.  [Martin Scharrer]

****	Fix SystemVerilog parameterized defines with `` expansion,
	and fix extra whitespace inserted on substitution. [Vladimir Matveyenko]

****	Fix missing uwire keyword in Verilog::Language. [Jonathan David]

****	Fix parse error on min:typ:max delay pairs, bug34575. [Martin Scharrer]

* Verilog::Language 3.023 2008/02/12

****	Fix arrayed input/output pins.  [Thomas Ziller]

****	Fix "output reg unsigned" parse error.

* Verilog::Language 3.022 2008/01/15

***	Add ignoring of SystemVerilog enumerations.  [Thomas Ziller]

****	Fix begin_keywords 1800-2005 error introduced in last release.

* Verilog::Language 3.021 2008/01/07

****	Fix endclass keyword parsing.  [David Plumb]

****	Fix "://" parsing as ":/" operator instead of comment. [Mark Nodine]

* Verilog::Language 3.020 2007/12/03

**	Add SystemVerilog logic types.  [Thomas Ziller]
	(SystemVerilog support is still a work in progress).

***	Add SystemVerilog operators += ## @@ :: etc.

***	Add specify operators &&& => *>.  [Mark Nodine]

***	Add SystemVerilog times (10ns, etc).

****	Fix concatenates in for loop assignments.  [Mark Nodine]

****	Fix endmodule/endfunc callback line numbers.

* Verilog::Language 3.013 2007/10/18

****	Fix parsing module #(parameter x,y) declarations. [Oleg Rodionov]

****	Fix parsing system functions with empty parens. [Oleg Rodionov]

****	Fix Verilog::Netlist errors having wrong line number. [Oleg Rodionov]

* Verilog::Language 3.012 2007/09/10

**	Added Verilog::EditFiles module and vsplitmodule example.

* Verilog::Language 3.011 2007/07/31

***	Added event trigger -> operator. [Mark Nodine]

****	Remove preprocessor adding newlines before `line. [Mark Nodine]

* Verilog::Language 3.010 2007/07/18

***	Added Parser::endparse callback. [Mark Nodine]

***	Added SigParser::endmodule, endtaskfunc, and endcell callbacks.

****	Fix attachment of comments to proceeding cells. [David Chinnery]

* Verilog::Language 3.002 2007/07/16

***	Find functions now search backslash escaped names.  [David Chinnery]

***	Fix vrename breakage in 3.00* releases.  [David Price]

****	Fix SigParser::comment to call Parser::Comment. [Mark Nodine]

****	Fix Parser::unreadback to always return value. [Mark Nodine]

****	Fix g++ bug giving "out of memory" on Cygwin.  [Pongstorn]

* Verilog::Language 3.001 2007/06/20

****	Support V2K function/task argument lists.

****	Fix Preprocessor dropping some `line directives.  [Mark Nodine]

****	Fix Netlist "not found" errors on primitives, bug27624. [Jeff Trull]

* Verilog::Language 3.000 2007/06/12

** 	Note this is a MAJOR release that may have incompatibilities with
	earlier versions, although I've attempted to minimize problems.
	Please email any problems to the author.

**	Verilog::SigParser has been completely rewritten.  The good news is
	it understands almost the entire Verilog 2005 language.  The bad
	news is there are minor incompatibilities with previous versions,
	and the parser now errors out when it does not understand something
	rather than ignoring it.

***	The Verilog::SigParser->pin callback now passes "" as the pin name
	instead of "pin###" if connecting by position instead of by name.

***	Added Verilog::SigParser->funcsignal callback for variables declared
	inside a function or task.  bug26972.  [Mark Nodine]

***	Added Verilog::SigParser->instant callbacks for gate primitives.
	bug26969, bug27062. [Mark Nodine]

***	Added Verilog::SigParser->parampin callbacks for parameter connections
	to instantiations.

***	Added Verilog::SigParser->signal_decl callbacks for all module vars,
	including parameters and genvars.

***	Added Verilog::SigParser->signal_decl callback argument with
	initial values of parameters and wires. [Mark Nodine]

**	Verilog::Parser has been replaced with the front end of the
	SigParser.  The preproc and syscall callbacks were added

***	Require call to Verilog::Parser->eof() at the end of all parsers.

***	Changed Verilog::Parser->unreadback() method to not clear state.
	You must now call unreadback('') to clear the unreadback characters.

***	The long depreciated Verilog::Parse module has been removed.

****	Fixed Verilog::Parser mis-parsing spaces in numbers, bug27070.

****	Fixed Verilog::SigParser bug26141, bug26940, bug26968, bug26969,
	bug26970, bug26972, bug26997, bug27009, bug27010, bug27013,
	bug27036, bug27037, bug27039, bug27045, bug27062, bug27066,
	bug27067, bug27072.  [Mark Nodine, et al]

* Verilog::Language 2.380 2007/05/27

***	Added new Verilog-Perl.pod documentation overview.

***	Verilog::Parser and Verilog::SigParser objects must call the eof method
	to insure forward compatibility.

***	Vpm $info etc have been removed, now only $uinfo, etc are supported.
	This avoids conflict with SystemVerilog $error function.  [Tad Truex]

***	Verilog::Language keywords now uses the `begin_keywords standard names.

***	Added Verilog::Language::number_bitvector and number_bigint for returning
	Bit::Vector and Math::BigInt objects.  bug26967.  [Mark Nodine]

****	Fix --help to use Pod::Usage instead of depreciated pod2text.

****	Ignore quotes inside `protected/`endprotected blocks.

****	Drop end-of-file ctrl-Z's when preprocessing input.

* Verilog::Language 2.373 2007/04/02

***     Fix vppp breaking with Getopt::Long 2.36.  [Andreas J. König]

****	Fix modules without any ports causing lost declarations.  [Mark Nodine]

* Verilog::Language 2.372 2007/02/28

***	Add include_open_nonfatal option to Preproc and Netlist.  [Eric Miller]

****	Fix bug24552; Verilog::Module::new_net now defaults net type
	to 'wire'. [Takeo Komiyama]

* Verilog::Language 2.371 2007/01/23

***	Fix bug24345; supply statements cause lint warnings.  [Jeff Trull]

* Verilog::Language 2.370 2007/01/10

***	Fix bug24248; reg/tri/supply* declarations, etc are now stored in Net
	structures as the declared type, instead of as 'wire'.  [Jeff Trull]

***	Fix bug13462; parse {} concatenations in pin connections. [Jeff Trull]

***	Remove backslashes in quoted symbols when they aren't needed.

****	Fix vpm deleting output when file moved between directories.

* Verilog::Language 2.361 2006/10/02

**	Attach Verilog comments to Netlist objects.  [Monte Becker]

***	Add parameters to Verilog::Parser instant callback.  [Monte Becker]

* Verilog::Language 2.360 2006/09/14

***	Added Preproc keep_whitespace=>0 option to delete whitespace.

***	Preprocessor now strips all DOS carrage returns.

***	Allow Verilog::Getopt::file_path to resolve module_dir and/or incdirs.
	Use only module_dir to resolve Netlist modules.  [by John Tseng]

****    Vrename --crypt now uses lower case random identifiers for readability.

****	Fix DOS carrage returns in multiline defines.  [Ralf Karge]

* Verilog::Language 2.352 2006/08/22

***	Fix compile errors under Cygwin.  [Mattan Tsachi]

* Verilog::Language 2.351 2006/06/08

***     Add vhier --language option.  [Sean Nazareth]

****	Fix Getopt::file_path when dir names match file names. [by John Tseng]

* Verilog::Language 2.350 2006/05/19

***	Vpm now emits $timeformat when passed the --timeformat-units switch.