bcd99.vhd

设计了一个计数范围是0到99的BCD计数器并可以显示出来的

--******************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--******************************************************
ENTITY BCD99 IS
	PORT(
			CLK1,CLK2:  IN  STD_LOGIC;		
			CLR      :  IN  STD_LOGIC;				
			ENA      :  IN  STD_LOGIC;
            SEGOUT   :  OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
            SELOUT   :  OUT STD_LOGIC_VECTOR(7 DOWNTO 0)				
		);
END BCD99;
--*******************************************************
ARCHITECTURE ART OF BCD99 IS
  COMPONENT COUNTER10
	PORT(
			CLK	     :  IN  STD_LOGIC;		
			CLR      :  IN  STD_LOGIC;				
			ENA      :  IN  STD_LOGIC;
            CY10     :  OUT STD_LOGIC;
            SUM      :  OUT STD_LOGIC_VECTOR(3 DOWNTO 0)				
		);
  END COMPONENT;
  COMPONENT DISCTRL
	PORT(
		 CLK     : IN	STD_LOGIC;
		 DATAIN	: IN 	STD_LOGIC_VECTOR(11 downto 0);
		 SEG     : OUT	STD_LOGIC_VECTOR(6 downto 0);
         SEL     : OUT	STD_LOGIC_VECTOR(7 downto 0)
       );
  END COMPONENT;
  SIGNAL CAY1,CAY2,CAY3 :STD_LOGIC;
  SIGNAL DATA : STD_LOGIC_VECTOR(11 downto 0);
  BEGIN
  U1:COUNTER10 PORT MAP(CLK=>CLK1,CLR=>CLR,ENA=>ENA,CY10=>CAY1,SUM=>DATA(3 DOWNTO 0));
  U2:COUNTER10 PORT MAP(CLK=>CAY1,CLR=>CLR,ENA=>ENA,CY10=>CAY2,SUM=>DATA(7 DOWNTO 4));
  U3:COUNTER10 PORT MAP(CLK=>CAY2,CLR=>CLR,ENA=>ENA,CY10=>CAY3,SUM=>DATA(11 DOWNTO 8));
  U4:DISCTRL   PORT MAP(CLK=>CLK2,DATAIN=>DATA,SEG=>SEGOUT,SEL=>SELOUT);
END ART;