shm.rpt

用TCD1501D驱动器产生CCD驱动的6个输出信号RS、CP、SP、SH以及Φ1、Φ2脉冲

         #  _LC061 & !P19 & !P110 & !P111 & !P112 &  P113 & !P114 &  P115
         #  _LC061 & !P113 & !P114 &  P115
         #  _LC061 & !P115;

-- Node name is ':12' = 'P111' 
-- Equation name is 'P111', location is LC037, type is buried.
P111     = DFFE( _EQ014 $  GND, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ014 =  _LC060 & !P17 & !P18 &  P19 & !P110 & !P111 & !P112 &  P113 & 
             !P114 &  P115
         #  _LC060 & !P19 & !P110 & !P111 & !P112 &  P113 & !P114 &  P115
         #  _LC060 & !P113 & !P114 &  P115
         #  _LC060 & !P115;

-- Node name is ':11' = 'P112' 
-- Equation name is 'P112', location is LC036, type is buried.
P112     = DFFE( _EQ015 $  GND, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ015 =  _LC058 & !P17 & !P18 &  P19 & !P110 & !P111 & !P112 &  P113 & 
             !P114 &  P115
         #  _LC058 & !P19 & !P110 & !P111 & !P112 &  P113 & !P114 &  P115
         #  _LC058 & !P113 & !P114 &  P115
         #  _LC058 & !P115;

-- Node name is ':10' = 'P113' 
-- Equation name is 'P113', location is LC035, type is buried.
P113     = DFFE( _EQ016 $  GND, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ016 =  _LC057 & !P17 & !P18 &  P19 & !P110 & !P111 & !P112 &  P113 & 
             !P114 &  P115
         #  _LC057 & !P19 & !P110 & !P111 & !P112 &  P113 & !P114 &  P115
         #  _LC057 & !P113 & !P114 &  P115
         #  _LC057 & !P115;

-- Node name is ':9' = 'P114' 
-- Equation name is 'P114', location is LC034, type is buried.
P114     = DFFE( _EQ017 $  GND, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ017 =  _LC053 & !P17 & !P18 &  P19 & !P110 & !P111 & !P112 &  P113 & 
             !P114 &  P115
         #  _LC053 & !P19 & !P110 & !P111 & !P112 &  P113 & !P114 &  P115
         #  _LC053 & !P113 & !P114 &  P115
         #  _LC053 & !P115;

-- Node name is ':8' = 'P115' 
-- Equation name is 'P115', location is LC033, type is buried.
P115     = DFFE( _EQ018 $  GND, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ018 =  _LC056 & !P17 & !P18 &  P19 & !P110 & !P111 & !P112 &  P113 & 
             !P114 &  P115
         #  _LC056 & !P19 & !P110 & !P111 & !P112 &  P113 & !P114 &  P115
         #  _LC056 & !P113 & !P114 &  P115
         #  _LC056 & !P115;

-- Node name is 'SH' = 'SH0' 
-- Equation name is 'SH', location is LC049, type is output.
 SH      = DFFE( _EQ019 $  GND, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ019 =  P13 & !P14 & !P15 & !P16 & !P17 & !P18 & !P19 & !P110 & !P111 & 
             !P112 & !P113 & !P114 & !P115
         #  P19 &  P113 &  P115 &  SH &  _X001
         #  P113 &  P115 &  SH &  _X002
         #  P114 &  P115 &  SH;
  _X001  = EXP(!P17 & !P18);
  _X002  = EXP(!P110 & !P111 & !P112);

-- Node name is ':7' = 'SH1' 
-- Equation name is 'SH1', location is LC051, type is buried.
SH1      = DFFE( _EQ020 $ !P115, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ020 =  _X003 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009 & 
              _X010 &  _X011;
  _X003  = EXP(!P10 & !P12 & !P13 &  P14 & !P15 & !P16 & !P17 & !P18 & !P19 & 
             !P110 & !P111 & !P112 & !P113 & !P114 & !P115);
  _X004  = EXP(!P11 & !P12 & !P13 &  P14 & !P15 & !P16 & !P17 & !P18 & !P19 & 
             !P110 & !P111 & !P112 & !P113 & !P114 & !P115);
  _X005  = EXP( P11 &  P12 & !P14 & !P15 & !P16 & !P17 & !P18 & !P19 & !P110 & 
             !P111 & !P112 & !P113 & !P114 & !P115);
  _X006  = EXP( P10 &  P12 & !P14 & !P15 & !P16 & !P17 & !P18 & !P19 & !P110 & 
             !P111 & !P112 & !P113 & !P114 & !P115);
  _X007  = EXP( P13 & !P14 & !P15 & !P16 & !P17 & !P18 & !P19 & !P110 & !P111 & 
             !P112 & !P113 & !P114 & !P115);
  _X008  = EXP(!P17 & !P18 & !P110 & !P111 & !P112 & !P114 &  P115);
  _X009  = EXP(!P19 & !P110 & !P111 & !P112 & !P114 &  P115);
  _X010  = EXP(!P113 & !P114 &  P115);
  _X011  = EXP( P115 & !SH1);

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( P11 $  P10);

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC018', type is buried 
_LC018   = LCELL( P12 $  _EQ021);
  _EQ021 =  P10 &  P11;

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC052', type is buried 
_LC052   = LCELL( P13 $  _EQ022);
  _EQ022 =  P10 &  P11 &  P12;

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC054', type is buried 
_LC054   = LCELL( P14 $  _EQ023);
  _EQ023 =  P10 &  P11 &  P12 &  P13;

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC059', type is buried 
_LC059   = LCELL( P15 $  _EQ024);
  _EQ024 =  P10 &  P11 &  P12 &  P13 &  P14;

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC055', type is buried 
_LC055   = LCELL( P16 $  _EQ025);
  _EQ025 =  P10 &  P11 &  P12 &  P13 &  P14 &  P15;

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC064', type is buried 
_LC064   = LCELL( P17 $  _EQ026);
  _EQ026 =  P10 &  P11 &  P12 &  P13 &  P14 &  P15 &  P16;

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder1|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC063', type is buried 
_LC063   = LCELL( P18 $  _EQ027);
  _EQ027 =  P10 &  P11 &  P12 &  P13 &  P14 &  P15 &  P16 &  P17;

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder1|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC062', type is buried 
_LC062   = LCELL( P19 $  _EQ028);
  _EQ028 =  P10 &  P11 &  P12 &  P13 &  P14 &  P15 &  P16 &  P17 &  P18;

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder1|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC061', type is buried 
_LC061   = LCELL( P110 $  _EQ029);
  _EQ029 =  P10 &  P11 &  P12 &  P13 &  P14 &  P15 &  P16 &  P17 &  P18 & 
              P19;

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder1|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC060', type is buried 
_LC060   = LCELL( P111 $  _EQ030);
  _EQ030 =  P10 &  P11 &  P12 &  P13 &  P14 &  P15 &  P16 &  P17 &  P18 & 
              P19 &  P110;

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder1|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC058', type is buried 
_LC058   = LCELL( P112 $  _EQ031);
  _EQ031 =  P10 &  P11 &  P12 &  P13 &  P14 &  P15 &  P16 &  P17 &  P18 & 
              P19 &  P110 &  P111;

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder1|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC057', type is buried 
_LC057   = LCELL( P113 $  _EQ032);
  _EQ032 =  P10 &  P11 &  P12 &  P13 &  P14 &  P15 &  P16 &  P17 &  P18 & 
              P19 &  P110 &  P111 &  P112;

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder1|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC053', type is buried 
_LC053   = LCELL( P114 $  _EQ033);
  _EQ033 =  P10 &  P11 &  P12 &  P13 &  P14 &  P15 &  P16 &  P17 &  P18 & 
              P19 &  P110 &  P111 &  P112 &  P113;

-- Node name is '|LPM_ADD_SUB:1093|addcore:adder|addcore:adder1|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC056', type is buried 
_LC056   = LCELL( P115 $  _EQ034);
  _EQ034 =  P10 &  P11 &  P12 &  P13 &  P14 &  P15 &  P16 &  P17 &  P18 & 
              P19 &  P110 &  P111 &  P112 &  P113 &  P114;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                        d:\program files\texteditor\shm.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,186K